TY - JOUR N2 - This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area. L1 - http://journals.pan.pl/Content/110229/PDF/42.pdf L2 - http://journals.pan.pl/Content/110229 PY - 2019 IS - No 2 EP - 318 DO - 10.24425/ijet.2019.126316 KW - EDAC KW - ALU KW - speed KW - block reduction KW - power KW - slew rate A1 - Kavitha, S. A1 - Hashim, Fazida Hanim A1 - Kamal, Noorfazila PB - Polish Academy of Sciences Committee of Electronics and Telecommunications VL - vol. 65 DA - 2019.06.13 T1 - A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks SP - 313 UR - http://journals.pan.pl/dlibra/publication/edition/110229 T2 - International Journal of Electronics and Telecommunications ER -