TY - JOUR N2 - In this paper we discuss some physical limits for scaling of transistors and conducting paths inside of semiconductor integrated circuits (ICs). Since 40 years only a semiconductor technology, mostly the CMOS and the TTL technologies, are used for fabrication of integrated circuits on an industrial scale. Miniaturization of electronic devices in integrated circuits has technological limits and physical limits as well. In 2010 best parameters of commercial ICs shown the Intel Core i5-670 processor manufactured in the technology of 32 nm. Its clock frequency in turbo mode is 3.73 GHz. A forecast of the development of the semiconductor industry (ITRS 2011) predicts that sizes of electronic devices in ICs circuits will be smaller than 10 nm in the next 10 years. At least 5 physical effects should be taken into account if we discuss limits of scaling of integrated circuits. L1 - http://journals.pan.pl/Content/89954/PDF/nawrocki_mms.pdf L2 - http://journals.pan.pl/Content/89954 PY - 2012 IS - No 3 EP - 488 DO - 10.2478/v10178-012-0041-8 KW - nanostructure KW - quantum effect KW - integrated circuits. A1 - Nawrocki, Waldemar A1 - Shukrinov, Yury M. PB - Polish Academy of Sciences Committee on Metrology and Scientific Instrumentation DA - 2012 T1 - Some quantum limits for scaling of electronic devices – estimations and measurements SP - 481 UR - http://journals.pan.pl/dlibra/publication/edition/89954 T2 - Metrology and Measurement Systems ER -