Szczegóły

Tytuł artykułu

Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array Blocks

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2010

Numer

No 1

Autorzy publikacji

Wydział PAN

Nauki Techniczne

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

2010

Identyfikator

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

Referencje

Adamski M. and Węgrzyn M., "Design of reconfigurable logic controllers from petri net-based specifications," in <i>Discrete-Event System Design - DESDes '09: preprints of the 4th IFAC Workshop</i>, University of Valencia, University of Zielona Góra. Gandia Beach, Hiszpania: [B. m.], 2009, pp. 233-238. ; G. Borowik, T. Łuba, and P. Tomaszewicz, "A notion of r-admissibility and its application in logic synthesis," in <i>Discrete-Event System Design - DESDes '09: preprints of the 4th IFAC Workshop</i>, University of Valencia, University of Zielona Góra. Gandia Beach, Hiszpania: [B. m.], 2009, pp. 233-238. ; Wiśniewski R. (2009), Syntheis of Compositional Microprogram Control Units for Programmable Devices. ; Harel D. (1987), Statecharts: A Visual Formalism for Complex Systems, Science of Computer Programming, 8, 231. ; <i>Unified Modeling Language Specification. Version 1.4.2. ISO/IEC 19501</i>, Object Management Group, OMG, 250 First Avenue, Needham, MA 02494, U. S. A., Apr. 2005. [Online]. Available: <a target="_blank" href='http://www.omg.org/cgi-bin/doc?formal/05-04-01'>http://www.omg.org/cgi-bin/doc?formal/05-04-01</a> ; Drusinsky D. (1989), Using Statecharts for Hardware Description and Synthesis, IEEE Transaction on Coputer-Aided Design, 8, 7, 798. ; Drusinsky-Yoresh D. (1991), A State Assignment Procedure for Single-Block Implementation of State Chart, IEEE Transaction on Coputer-Aided Design, 10, 12, 1569. ; Ramesh S. (1999), Efficient Translation of Statecharts to Hardware Circuits, null, 384. ; <i>STATEMATE Magnum Code Generation Guide.</i>, I-Logix Inc., 3 Riverside Drive, Andover, MA 01810 U. S. A., 2001. ; Buchenrieder K. (1996), Mapping statechart models onto an FPGA-based ASIP architecture, Proc. EURO-DAC '96, 184. ; G. Łabiak, "HiCoS Homepage," http://www.uz.zgora.pl/~glabiak, 2004. [Online]. Available: <a target="_blank" href='http://www.uz.zgora.pl/~glabiak'>http://www.uz.zgora.pl/~glabiak</a> ; Łabiak G. (2003), From UML statecharts to FPGA - the HiCoS approach, null, 354. ; G. Łabiak, "From statecharts to FSM-description - transformation by means of symbolic methods." in <i>Discrete-Event System Design - DESDes '06. A proceedings volume from the 3rd IFAC Workshop</i>, Rydzyna n. Leszno, Oct. 2006, pp. 161-166. ; Borowik G. (2007), Cost-efficient synthesis for sequential circuits implemented using embedded memory blocks of fpga's, null, 99. ; Borowik G. (2008), Improved state encoding for fsm implementation in fpga structures with embedded memory blocks, Electronics and Telecommunications Quarterly, 54, 1, 9. ; M. von der Beeck (1994), A Comparison of Statecharts Variants, null, 128. ; Adamski M. (1991), FPGAs, 296. ; G. Łabiak, <i>The use of hierarchical model of concurrent automaton in digital controller design, in polish, ISBN: 83-89712-42-3</i>, ser. Prace Naukowe z Automatyki i Informatyki. Zielona Góra: Oficyna Wydawnicza Uniwersytetu Zielonogórskiego, 2005, vol. VI. ; E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Department of Electrical Engineering and Computer Science, University of California, Berkeley, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, Tech. Rep. UCB/ERL M92/41, May 1992. ; F. Somenzi, "CUDD: CU Decision Diagram Package Release 2.4.0." WWW, Feb. 2004, department of Electrical and Computer Engineering University of Colorado at Boulder. [Online]. Available: <a target="_blank" href='http://vlsi.colorado.edu/fabio/CUDD/cuddIntro.html'>http://vlsi.colorado.edu/fabio/CUDD/cuddIntro.html</a> ; Łabiak G. (2005), Design of Embedded Control Systems, 73. ; Hopcroft J. (2000), Introduction to Automata Theory, Languages and Computation. ; Łuba T. (2009), Synthesis of finite state machines for implementation with programmable structures, Electronics and Telecommunications Quarterly, 55, 2. ; Rawski M. (2005), An application of functional decomposition in rom-based fsm implementation in fpga devices, Journal of Systems Architecture, 51, 424. ; Selvaraj H. (2002), FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition, null, 355. ; Brzozowski J. (2003), Decomposition of boolean functions specified by cubes, Journal of Multi-Valued Logic & Soft Computing, 9, 377.

DOI

10.2478/v10177-010-0002-7

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