Evaluation Scheme for NoC-based CMP with Integrated Processor Management System

Journal title

International Journal of Electronics and Telecommunications




No 2

Publication authors

Divisions of PAS

Nauki Techniczne


Evaluation Scheme for NoC-based CMP with Integrated Processor Management System With the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.


Polish Academy of Sciences Committee of Electronics and Telecommunications




ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)


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