Architecture Design of The Hardware H.264/AVC Video Decoder

Journal title

International Journal of Electronics and Telecommunications




vol. 56


No 3

Publication authors

Divisions of PAS

Nauki Techniczne


Polish Academy of Sciences Committee of Electronics and Telecommunications




ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)


Chen T.-W. (2005), Architecture design of h.264/avc decoder with hybrid task pipelining for high definition videos, IEEE International Symposium on Circuits and Systems 2005, 3, 2931. ; Chen T.-C. (2006), Algorithm analysis and architecture design for hdtv applications - a look at the h.264/avc video compressor system, IEEE Circuits and Devices Magazine, 22, 22. ; Eeckhaut H. (2006), Optimizing the critical loop in the h.264/avc cabac decoder, null, 113. ; Hu Y. (2004), A high definition h.264/avc hardware video decoder core for multimedia soc's, null, 385. ; Huang Y.-W. (2005), Analysis, Fast Algorithm, and VLSI Architecture Design for h.264/avc Intra Frame Coder, IEEE Transactions on Circuits and Systems for Video Technology, 15, 378. ; <i>Recommendation ITU-T H.264(2007) — Corrigendum 1</i>, Joint Video Team of ITU-T VCEG and ISO/IEC MPEG, January 2009. ; <i>Report of The Formal Verification Tests on AVC (ISO/IEC 14496-10 — ITU-T Rec. H.264)</i>, JVT, Test and Video Group, December 2003, Waikoloa. ; Lin C.-C. (2007), A 160k gates/4.5 kb sram h.264 video decoder for hdtv applications, IEEE Journal of Solid-State Circuits, 42, 1, 170. ; Marpe D. (2005), H.264/MPEG4-AVC Fidelity Range Extensions: Tools, Profiles, Performance, and Application Areas, null, 1, 593. ; Richardson I. (2003), H.264 and MPEG-4 Video Compression. ; Staehler W. (2006), Architecture of an hdtv Intraframe Predictor for a h.264 Decoder, null, 228. ; Tsai C.-H. (2005), Algorithm and architecture optimization for full-mode encoding of h.264/avc intra prediction, null, 1, 47.