Details

Title

Programmable, Asynchronous, Triangular Neighborhood Function for Self-Organizing Maps Realized on Transistor Level

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2010

Volume

vol. 56

Numer

No 4

Publication authors

Divisions of PAS

Nauki Techniczne

Description

International Journal of Electronics and Telecommunications (IJET, eISSN 2300-1933, untill 2013 also print ISSN 2081-8491) is a periodical of Electronics and Telecommunications Committee of Polish Academy of Sciences and it is published by Warsaw Science Publishers of PAS. It continues tradition of the Electronics and Telecommunications Quarterly (ISSN 0867-6747) established in 1955 as the Rozprawy Elektrotechniczne. The IJET is a scientific periodical where papers present the results of original, theoretical, experimental and reviewed works. They consider widely recognized aspects of modern electronics, telecommunications, microelectronics, optoelectronics, radioelectronics and medical electronics.

The authors are outstanding scientists, well‐known experienced specialists as well as young researchers – mainly candidates for a doctor's degree. The papers present original approaches to problems, interesting research results, critical estimation of theories and methods, discuss current state or progress in a given branch of technology and describe development prospects. All the papers published in IJET are reviewed by international specialists who ensure that the publications are recognized as author's scientific output.

The printed periodical is distributed among all those who deal with electronics and telecommunications in national scientific centers as well as in numeral foreign institutions, and it is subscribed by many specialists and libraries. Its electronic version is available at http://ijet.pl.

The papers received are published within half a year if the cooperation between author and the editorial staff is efficient. The papers may be submitted to the editorial office by the journal web page http://ijet.pl.

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2010

Identifier

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

References

Osowski S. (2001), ECG beat recognition using fuzzy hybrid neural network, IEEE Transactions on Biomedical Engineering, 48, 11. ; Wismüller A. (2002), Cluster analysis of biomedical image time-series, International Journal of Computer Vision, 46, 2. ; Kohonen T. (2001), Self-Organizing Maps, doi.org/10.1007/978-3-642-56927-2 ; Boniecki P. (2005), The kohonen neural network in classification problems solving in agricultural engineering, Journal of Research and Applications in Agricultural Engineering, 50, 1, 37. ; Mokriš I. (2004), Decreasing the feature space dimension by kohonen self-organizing maps, null. ; Li F. (2009), A compact current mode neuron circuit with gaussian taper learning capability, IEEE International Symposium on Circuits and Systems, 2129, doi.org/10.1109/ISCAS.2009.5118216 ; Abuelma'ati M. (2006), A reconfigurable gaussian/ triangular basis function computation circuit, null, 232. ; Masmoudi D. (2002), A subtreshold mode programmable implementation of the gaussian function for rbf neural networks applications, null, 454. ; Długosz R. (2010), Programmable triangular neighborhood functions of kohonen self-organizing maps realized in CMOS technology, null, 529. ; Długosz R. (2008), CMOS, programmable, asynchronous neighborhood mechanism for wtm kohonen neural network, null, 197. ; Długosz R. (2010), Realization of a conscience mechanism in CMOS implementation of winner takes all neural networks, IEEE Transactions on Neural Networks, 21, 6, 961. ; Dubois P. (2009), Ad hoc wireless sensor networks for exploration of solar-system bodies, Acta Astronautica, 64, 5-6, 626. ; Długosz R. (2009), Optimization of the neighborhood mechanism for hardware implemented kohonen neural networks, null, 565. ; V. Peiris, "Mixed analog-digital VLSI implementation of a kohonen neural network," Ph.D. dissertation, Ph.D thesis, Ecole Polytechnique Fédérale de Lausanne (EPFL), 1994. ; Chang C. (2005), A review of 0.18m full adder performances for tree structured arithmetic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, 6, 686.

DOI

10.2478/v10177-010-0048-6

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