Szczegóły

Tytuł artykułu

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2010

Wolumin

vol. 56

Numer

No 4

Autorzy publikacji

Wydział PAN

Nauki Techniczne

Opis

International Journal of Electronics and Telecommunications (IJET, eISSN 2300-1933, untill 2013 also print ISSN 2081-8491) is a periodical of Electronics and Telecommunications Committee of Polish Academy of Sciences and it is published by Warsaw Science Publishers of PAS. It continues tradition of the Electronics and Telecommunications Quarterly (ISSN 0867-6747) established in 1955 as the Rozprawy Elektrotechniczne. The IJET is a scientific periodical where papers present the results of original, theoretical, experimental and reviewed works. They consider widely recognized aspects of modern electronics, telecommunications, microelectronics, optoelectronics, radioelectronics and medical electronics.

The authors are outstanding scientists, well‐known experienced specialists as well as young researchers – mainly candidates for a doctor's degree. The papers present original approaches to problems, interesting research results, critical estimation of theories and methods, discuss current state or progress in a given branch of technology and describe development prospects. All the papers published in IJET are reviewed by international specialists who ensure that the publications are recognized as author's scientific output.

The printed periodical is distributed among all those who deal with electronics and telecommunications in national scientific centers as well as in numeral foreign institutions, and it is subscribed by many specialists and libraries. Its electronic version is available at http://ijet.pl.

The papers received are published within half a year if the cooperation between author and the editorial staff is efficient. The papers may be submitted to the editorial office by the journal web page http://ijet.pl.

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

2010

Identyfikator

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

Referencje

Gardner F. (2005), Phaselock techniques. ; Tierno J. (2008), A wide power supply range, wide tuning range, all static cmos all digital pll in 65 nm soi, IEEE Journal of Solid-State Circuits, 43, 42. ; Arakali A. (2008), Supply-noise mitigation techniques in phaselocked loops, null. ; Brownlee M. (2006), A 0.5-ghz to 2.5-ghz pll with fully differential supply regulated tuning, IEEE Journal of Solid-State Circuits, 41, 2720. ; Cao Z. (2008), A 0.4 ps-rms-jitter 13 ghz ring-oscillator pll using phase-noise preamplification, IEEE Journal of Solid-State Circuits, 43, 2079. ; Jung W. (2007), A 1.2mw 0.02mm2 2ghz current-controlled pll based on a self-biased voltage-to-current converter, null. ; Mansuri M. (2003), A low-power adaptive bandwidth pll and clock buffer with supply-noise compensation, IEEE Journal of Solid-State Circuits, 38, 1804. ; Yan G. (2005), A self-biased pll with current-mode filter for clock generation, null. ; Razavi B. (2001), Design of analog CMOS itegrated circuits. ; Baker J. (2005), CMOS circuit design, layout and simulation. ; Mansuri M. (2002), Fast frequency acquisition phasefrequency detectors for gsamples/s phase-locked loops, IEEE Journal of Solid-State Circuits, 37, 1331. ; Razavi B. (1996), Monolithic phase-locked loops and clock recovery circuits. ; Huang Q. (1996), Speed optimization of edge-triggered cmos circuits for gigaherz single-phase clocks, IEEE Journal of Solid-State Circuits, 31, 456. ; <i>Jitter measurements using SpecreRF</i>, Cadence Design Systems. ; A. Zaziabl, "Design of integrated phase-locked loop module in submicron process," Master's thesis, AGH University od Science and Technology, Cracow, Poland, June 2009.

DOI

10.2478/v10177-010-0055-7

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