Details

Title

Fast Determination of Similarity Between Two Vectors by Means of Analog CMOS Technique

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2010

Volume

vol. 56

Numer

No 4

Publication authors

Divisions of PAS

Nauki Techniczne

Description

International Journal of Electronics and Telecommunications (IJET, eISSN 2300-1933, untill 2013 also print ISSN 2081-8491) is a periodical of Electronics and Telecommunications Committee of Polish Academy of Sciences and it is published by Warsaw Science Publishers of PAS. It continues tradition of the Electronics and Telecommunications Quarterly (ISSN 0867-6747) established in 1955 as the Rozprawy Elektrotechniczne. The IJET is a scientific periodical where papers present the results of original, theoretical, experimental and reviewed works. They consider widely recognized aspects of modern electronics, telecommunications, microelectronics, optoelectronics, radioelectronics and medical electronics.

The authors are outstanding scientists, well‐known experienced specialists as well as young researchers – mainly candidates for a doctor's degree. The papers present original approaches to problems, interesting research results, critical estimation of theories and methods, discuss current state or progress in a given branch of technology and describe development prospects. All the papers published in IJET are reviewed by international specialists who ensure that the publications are recognized as author's scientific output.

The printed periodical is distributed among all those who deal with electronics and telecommunications in national scientific centers as well as in numeral foreign institutions, and it is subscribed by many specialists and libraries. Its electronic version is available at http://ijet.pl.

The papers received are published within half a year if the cooperation between author and the editorial staff is efficient. The papers may be submitted to the editorial office by the journal web page http://ijet.pl.

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2010

Identifier

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

References

Ahalt S. (1990), Competitive learning algorithms for vector quantization, Neural Networks, 3, 131. ; Cauwenberghs G. (1999), Learning on silicon: Adaptive VLSI Neural Systems. ; Chen S.-L. (2008), A variable control system for wireless body sensor network, null, 2034. ; Chen Y. (1992), ANN with two-dendrite neurons and its weight initialization, null, 139. ; DeSieno D. (1988), Adding a conscience to competitive learning, null, 1, 117. ; Długosz R. (2006), New binary-tree-based Winner-Takes-All circuit for learning on silicon Kohonen's networks, null. ; Fakhraie S. (1997), VLSI-compatible implementations for artificial neural networks, doi.org/10.1007/978-1-4615-6311-2 ; Gatet L. (2009), Comparison between analog and digital neural network implementations for range-finding applications, IEEE Trans. Neural Netw, 20, 3. ; Holler M. (1989), An electrically trainable artificial neural network (ETANN) with 10240 ‘floating gate’ synapses, null, 191. ; Linares-Barranco B. (1993), A CMOS analog adaptive BAM with on-chip learning and weight refreshing, IEEE Trans. Neural Netw, 4, 3, 445. ; Macq D. (1993), Analog implementation of a Kohonen map with on-chip learning, IEEE Trans. Neural Netw, 4, 3, 456. ; Rajah A. (2004), ASIC design of a Kohonen Neural Network microchip, null, 148. ; Talaśka T. (2007), Adaptive weight change mechanism for Kohonens's Neural Network implemented in CMOS 0:18μm technology, null, 151. ; Wojtyna R. (2005), Simple CMOS transconductance-mode differential squarer, null, 171. ; Wojtyna R. (2006), Current-mode analog square rooter for hardware neuroprocessing, null. ; Wojtyna R. (2007), CMOS transconductance-mode analog circuit for fast determining Euclidean distance, Elektronika, 4, 65. ; Wojtyna R. (2009), Current-mode analog memory with extended storage time for hardware-implemented neural networks, Elektronika, 3, 34. ; Wojtyna R. (2004), Improved power-saving synapse for adaptive neuroprocessing on silicon, null, 27. ; Kohonen T. (2001), Self-Organizing Maps, doi.org/10.1007/978-3-642-56927-2

DOI

10.2478/v10177-010-0056-6

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