Details

Title

Methodology for Implementing Scalable Run-Time Reconfigurable Devices

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2011

Volume

vol. 57

Numer

No 2

Publication authors

Divisions of PAS

Nauki Techniczne

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2011

Identifier

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

References

Sanchez E. (2007), PERPLEXUS: Pervasive computing framework for modeling complex virtually-unbounded systems, null, 587. ; Upegui A. (2007), Dynamic routing on the ubichip: Toward synaptogenetic neural networks, null, 587. ; Thoma Y. (2007), Self-replication mechanism by means of selfreconfiguration, null. ; Moreno J. (2009), Synchronous digital implementation of the AER communication scheme for emulating large-scale spiking neural networks models, null, 189. ; Moreno J. (2009), A reconfigurable architecture for emulating large-scale bio-inspired systems, null, 126. ; Bhasker J. (2009), Static Timing Analysis for Nanometer Designs: A Practical Approach. ; "Si2 liberty syntax extensions for characterization and validation specification v1.0 21," Silicon Integration Initiative, Inc., 2009. ; "Liberty user guide, vol. 1 version 2009.06," Synopsys, Inc., 2009. ; Keating M. (2007), Reuse Methodology Manual for System-on-a-Chip Designs. ; Shiple T. (1996), Constructive analysis of cyclic circuits, null, 328. ; Gupta A. (2005), Acyclic modeling of combinational loops, null, 343. ; "Encounter digital implementation system user guide product version 9.1," Cadence Design Systems, Inc., 2009. ; Bhatnagar H. (2001), Advanced ASIC Chip Synthesis Using Synopsys Design Compiler Physical Compiler and PrimeTime. ; Zuchowski P. (2002), Hybrid ASIC and FPGA architecture, null, 187. ; "Standard delay format specification, version 3.0," Open Verilog International, 1995.

DOI

10.2478/v10177-011-0025-8

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