Szczegóły

Tytuł artykułu

Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2011

Wolumin

vol. 57

Numer

No 2

Autorzy publikacji

Wydział PAN

Nauki Techniczne

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

2011

Identyfikator

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

Referencje

Brzozowski J. (2003), Decomposition of Boolean Functions Specified by Cubes, Journal of Multiple-Valued Logic and Soft Computing, 9, 377. ; Łuba T. (1995), A General Approach to Boolean Function Decomposition and its Applications in FPGA-Based Synthesis, VLSI Design, 3, 3-4, 289, doi.org/10.1155/1995/67208 ; Rawski M. (2007), Decomposition of Boolean Function Sets, Electronics and Telecommunications Quarterly, 53, 3, 231. ; Sasao T. (2001), Compact BDD Representations for Multiple-Output Functions and Their Application, null, 207. ; Scholl C. (2001), Functional Decomposition with Application to FPGA Synthesis. ; Ashenhurst R. (1959), The Decomposition of Switching Functions, null, 29, 74. ; Curtis H. (1962), A New Approach to the Design of Switching Circuits. ; Karp R. (1963), Functional Decomposition and Switching Circuit Design, SIAM Journal on Applied Mathematics, 11, 2, 291, doi.org/10.1137/0111022 ; Hartmanis J. (1966), Algebraic Structure Theory of Sequential Machines. ; Selvaraj H. (1998), Performance Oriented Decomposition Strategies for FPGA Based Technology Mapping, null. ; Rawski M. (2001), Functional Decomposition with an Efficient Input Support Selection for Sub-Functions Based on Information Relationship Measures, Journal of Systems Architecture, 47, 2, 137, doi.org/10.1016/S1383-7621(00)00062-X ; Jóźwiak L. (1997), Information Relationships and Measures: An Analysis Apparatus for Efficient Information System Synthesis, null, 13. ; Chojnacki A. (2011), High-Quality FPGA Designs Through Functional Decomposition with Sub-Function Input Support Selection Based on Information Relationship Measures, null, 409. ; Chojnacki A. (2000), An Effective and Efficient Method for Functional Decomposition of Boolean Functions Based on Information Relationships Measures, null. ; Lee C. (1959), Representation of Switching Circuits by Binary-Decision Diagrams, The Bell System Technical Journal, 985. ; Akers S. (1978), Binary Decision Diagrams, IEEE Transactions on Computers, 27, 6, 509, doi.org/10.1109/TC.1978.1675141 ; Bryant R. (1986), Graph-Based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, 35, 6, 677, doi.org/10.1109/TC.1986.1676819 ; Sasao T. (1996), Representations of Discrete Functions, doi.org/10.1007/978-1-4613-1385-4 ; Micheli G. (1994), Synthesis and Optimization of Digital Circuits. ; Nowicka M. (1999), FPGA-Based Decomposition of Boolean Functions, Algorithms and Implementation, Advanced Computer Systems, 502. ; Rawski M. (2007), Efficient Variable Partitioning Method for Functional Decomposition, Electronics and Telecommunications Quarterly, 53, 1, 63. ; M. Rawski, <i>Evolutionary Algorithms</i>. Intech, 2011, ch. Evolutionary Algorithms in Decomposition-Based Logic Synthesis. ; Rawski M. (2006), Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition, International Journal of Computational Intelligence and Applications, 6, 2, 257, doi.org/10.1142/S1469026806001988 ; Łuba T. (1995), Decomposition of Multiple-Valued Functions, null, 256. ; Lewandowski J. (2007), Application of Parallel Decomposition for Creation of Reduced Feed-Forward Neural Networks, null, 564. ; Selvaraj H. (2001), Functional Decomposition and Its Applications in Machine Learning and Neural Networks, International Journal of Computational Intelligence and Applications, 1, 3, 259, doi.org/10.1142/S1469026801000226 ; Chojnacki A. (2000), Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationship Measures, null. ; Łuba T. (1994), Multi-Level Logic Synthesis Based on Decomposition, Microprocessors and Microsystems, 18, 8, 429, doi.org/10.1016/0141-9331(94)90090-6 ; Borowik G. (2009), A Notion of R-Admissibility and its Application in Logic Synthesis, null, 207.

DOI

10.2478/v10177-011-0029-4

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