Details

Title

UML Modelling in Rigorous Design Methodology for Discrete Controllers

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2012

Volume

vol. 58

Numer

No 1

Publication authors

Divisions of PAS

Nauki Techniczne

Description

International Journal of Electronics and Telecommunications (IJET, eISSN 2300-1933, untill 2013 also print ISSN 2081-8491) is a periodical of Electronics and Telecommunications Committee of Polish Academy of Sciences and it is published by Warsaw Science Publishers of PAS. It continues tradition of the Electronics and Telecommunications Quarterly (ISSN 0867-6747) established in 1955 as the Rozprawy Elektrotechniczne. The IJET is a scientific periodical where papers present the results of original, theoretical, experimental and reviewed works. They consider widely recognized aspects of modern electronics, telecommunications, microelectronics, optoelectronics, radioelectronics and medical electronics.

The authors are outstanding scientists, well‐known experienced specialists as well as young researchers – mainly candidates for a doctor's degree. The papers present original approaches to problems, interesting research results, critical estimation of theories and methods, discuss current state or progress in a given branch of technology and describe development prospects. All the papers published in IJET are reviewed by international specialists who ensure that the publications are recognized as author's scientific output.

The printed periodical is distributed among all those who deal with electronics and telecommunications in national scientific centers as well as in numeral foreign institutions, and it is subscribed by many specialists and libraries. Its electronic version is available at http://ijet.pl.

The papers received are published within half a year if the cooperation between author and the editorial staff is efficient. The papers may be submitted to the editorial office by the journal web page http://ijet.pl.

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2012

Identifier

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

References

Adamski M. (2005), Design of embedded control systems. ; Łabiak G. (2010), Statechart-based controllers synthesis in fpga structures with embedded array blocks, International Journal of Electronics and Telecommunications, 56, 1, 13, doi.org/10.2478/v10177-010-0002-7 ; Doligalski M. (2007), Partial reconfiguration-oriented design of logic controllers, null, 6937, 10. ; Booch G. (1999), The Unified Modeling Language. User Guide. ; Clarke E. (1999), Model Checking. ; Misurewicz P. (1976), Lecture Notes. ; Gniewek L. (2004), Hardware implementation of fuzzy Petri net as a controller, IEEE Transactions on Systems, Man, and Cybernetics - Part B: Cybernetics, 34, 3, 1315, doi.org/10.1109/TSMCB.2003.822956 ; Doligalski M. (2010), Exceptions and deep history state handling using dual specification, Electrical Review, 9, 123. ; čabiak G. (2008), Concurrent processes synchronisation in statecharts for FPGA implementation, null, 59. ; Biliński K. (1994), Petri-net-based algorithms for parallel-controller synthesis, IEE Proceedings - Computers and Digital Techniques, 141, 6, 405, doi.org/10.1049/ip-cdt:19941508 ; Karatkevich A. (2007), Dynamic Analysis of Petri Net-Based Discrete Systems, 356. ; Bukowiec A. (2009), Partitioning of Mealy finite state machines, null, 21. ; Wegrzyn A. (2005), Parallel algorithm for computation of deadlocks and traps in Petri nets, null, 143. ; Gallier J. (1985), Logic for Computer Science: Foundations of Automatic Theorem Proving. ; Tkacz J. (2007), State machine type colouring of Petri net by means of using a symbolic deduction method, Measurement Automation and Monitoring, 53, 5, 120. ; Adamski M. (1993), Petri nets in ASIC design, Applied Mathematics and Computer Science, 3, 1, 169. ; Zwoliński M. (2004), Digital System Design with VHDL. ; Puczyńska M. (2000), Programowa implementacja konwersji sieci petriego na jezyk VHDL, null, 285.

DOI

10.2478/v10177-012-0004-8

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