Details

Title

Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2012

Numer

No 4

Publication authors

Divisions of PAS

Nauki Techniczne

Abstract

Abstract Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is helpful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2012

Identifier

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

DOI

10.2478/v10177-012-0046-y

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