Details

Title

Low-Power High-Speed Double Gate 1-bit Full Adder Cell

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2016

Numer

No 4

Publication authors

Divisions of PAS

Nauki Techniczne

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2016

Identifier

ISSN 2081-8491 (until 2012) ; eISSN 2300-1933 (since 2013)

References

Shalem (1999), and A novel low power energy recovery full adder cell in Proceedings Ninth Great Lakes Symposium on, VLSI IEEE, 380. ; Zimmermann (1997), Low - Power Logic Styles : CMOS versus Pass - Transistor Logic of Solid - State Circuits, IEEE Journal, 32. ; Kang (2003), CMOS digital integrated circuits Tata McGraw, Education. ; Hang (2002), Improved structure for adiabatic CMOS circuits design, Microelectronics journal, 33. ; Pettenghi (2008), Using multi - threshold threshold gates in RTD - based logic design : A case study, Microelectronics Journal, 39. ; Jeong (2008), Implementation of low power adder design and analysis based on power reduction technique, Microelectronics Journal, 39. ; Sundararajan (1999), Low power synthesis of dual threshold voltage CMOS VLSI circuits in : Proceedings of the international symposium on Low power electronics and design, ACM, 1999. ; Kumar (2016), An efficient low power - bit full adder using multi - threshold voltage scheme in of on Advancement of Computer Communication and Electrical Technology Francis Group, Proc, 1. ; Zhuang (1992), A new design of the CMOS full adder of solid - state circuits, IEEE journal, 27. ; Yuan (2013), Pass transistor with dual threshold voltage domino logic design using standby switch for reduced sub threshold leakage current, Microelectronics Journal, 44. ; Navi (2009), A novel low - power full - adder cell with new technique in designing logical gates based on static CMOS inverter, Microelectronics Journal, 40. ; Abbasalizadeh (2012), Full adder design with gig cell and independent double gate transistor in th Iranian Conference on, Electrical Engineering IEEE, 20, 130.

DOI

10.1515/eletel-2016-0045

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