Details

Title

FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach

Journal title

Bulletin of the Polish Academy of Sciences: Technical Sciences

Yearbook

2016

Numer

No 4 December

Keywords

General Engineering ; Computer Networks and Communications ; Atomic and Molecular Physics, and Optics ; Artificial Intelligence ; Information Systems

Divisions of PAS

Nauki Techniczne

Abstract

<jats:title>Abstract</jats:title><jats:p>Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much lower power consumption than is available from single and multicore CPUs and GPUs (graphics processing unit) in many computational problems. Unfortunately, the pure programming for FPGA using hardware description languages (HDL), like VHDL or Verilog, is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty, the high level synthesis (HLS) approach is promoted by main FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a bandwidth selection algorithm for kernel density estimation (KDE) using HLS and show techniques which were used to optimize the final FPGA implementation. We are also going to show that FPGA speedups, comparing to highly optimized CPU and GPU implementations, are quite substantial. Moreover, power consumption for FPGA devices is usually much less than typical power consumption of the present CPUs and GPUs.</jats:p>

Publisher

Polish Academy of Sciences

Date

2016

Identifier

ISSN 0239-7528, eISSN 2300-1917

DOI

10.1515/bpasts-2016-0091

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