Details

Title

Pipeline processing in low-density parity-check codes hardware decoder

Journal title

Bulletin of the Polish Academy of Sciences: Technical Sciences

Yearbook

2011

Numer

No 2 June

Publication authors

Divisions of PAS

Nauki Techniczne

Publisher

Polish Academy of Sciences

Date

2011

Identifier

ISSN 0239-7528, eISSN 2300-1917

References

Gallager R. (1963), Low-Density Parity-Check Codes. ; MacKay D. (1999), Good error-correcting codes based on very sparse matrices, IEEE Trans. Inf. Theory, 45, 2, 399, doi.org/10.1109/18.748992 ; Mansour M. (2003), High throughput LDPC decoders, IEEE Trans. VLSI Syst, 11, 6, 976, doi.org/10.1109/TVLSI.2003.817545 ; Zhong H. (2005), Block-LDPC: A practical LDPC coding system design approach, IEEE Trans. Circuits Syst. 1, 52, 4, 766, doi.org/10.1109/TCSI.2005.844113 ; Sułek W. (2009), Seed graph expansion for construction of structured LDPC codes, IEEE Int. Symposium on Wireless Communication Systems (ISWCS), 1, 216. ; Lin S. (2004), Error Control Coding: Fundamentals and Applications. ; Chen J. (2005), Reduced-complexity decoding of LDPC codes, IEEE Trans. on Communications, 53, 8, 1288, doi.org/10.1109/TCOMM.2005.852852 ; Mansour M. (2006), A turbo-decoding message-passing algorithm for sparse parity-check matrix codes, IEEE Trans. Signal Process, 54, 11, 4376, doi.org/10.1109/TSP.2006.880240 ; Mansour M. (2006), A 640-Mb/s 2048-Bit programmable LDPC decoder chip, IEEE J. Solid-State Circuits, 41, 3, 684, doi.org/10.1109/JSSC.2005.864133 ; Yang L. (2006), Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder, IEEE Trans. Circuits Syst. 1, 53, 4, 892, doi.org/10.1109/TCSI.2005.862074 ; Rovini M. (2005), VLSI design of a high-throughput multi-rate decoder for structured LDPC codes, DSD 2005 Euromicro Conf. Digital System Design, 1, 202, doi.org/10.1109/DSD.2005.77 ; Hu X.-Y. (2001), Efficient implementations of the sum-product algorithm for decoding LDPC codes, IEEE Globecom, 1, 1036. ; Sułek W. (2008), Code construction algorithm for architecture aware LDPC codes with low-error-floor, Proc. IEEE Region 8 Int. Conf. on Computational Technologies in Electrical and Electronics Engineering - SIBIRCON 2008, 1, 1. ; Hu X.-Y. (2005), Regular and irregular progressive edge-growth tanner graphs, IEEE Trans. Inf. Theory, 51, 1, 386, doi.org/10.1109/TIT.2004.839541 ; Chen J. (2002), Near optimum universal belief propagation based decoding of low-density parity check codes, IEEE Trans. on Communications, 50, 3, 406, doi.org/10.1109/26.990903

DOI

10.2478/v10175-011-0019-9

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