The paper presents a heuristic approach to the problem of analog circuit diagnosis. Different optimization techniques in the field of test point selection are discussed. Two new algorithms: SALTO and COSMO have been introduced. Both searching procedures have been implemented in a form of the expert system in PROLOG language. The proposed methodologies have been exemplified on benchmark circuits. The obtained results have been compared to the others achieved by different approaches in the field and the benefits of the proposed methodology have been emphasized. The inference engine of the heuristic algorithms has been presented and the expert system knowledge-base construction discussed.
A new soft-fault diagnosis approach for analog circuits with parameter tolerance is proposed in this paper. The approach uses the fuzzy nonlinear programming (FNLP) concept to diagnose an analog circuit under test quantitatively. Node-voltage incremental equations, as constraints of FNLP equation, are built based on the sensitivity analysis. Through evaluating the parameters deviations from the solution of the FNLP equation, it enables us to state whether the actual parameters are within tolerance ranges or some components are faulty. Examples illustrate the proposed approach and show its effectiveness.
While the Slope Fault Model method can solve the soft-fault diagnosis problem in linear analog circuit effectively, the challenging tolerance problem is still unsolved. In this paper, a proposed Normal Quotient Distribution approach was combined with the Slope Fault Model to handle the tolerances problem in soft-fault diagnosis for analog circuit. Firstly, the principle of the Slope Fault Model is presented, and the huge computation of traditional Slope Fault Characteristic set was reduced greatly by the elimination of superfluous features. Several typical tolerance handling methods on the ground of the Slope Fault Model were compared. Then, the approximating distribution function of the Slope Fault Characteristic was deduced and sufficient conditions were given to improve the approximation accuracy. The monotonous and continuous mapping between Normal Quotient Distribution and standard normal distribution was proved. Thus the estimation formulas about the ranges of the Slope Fault Characteristic were deduced. After that, a new test-nodes selection algorithm based on the reduced Slope Fault Characteristic ranges set was designed. Finally, two numerical experiments were done to illustrate the proposed approach and demonstrate its effectiveness.
This paper presents a novel strategy of fault classification for the analog circuit under test (CUT). The proposed classification strategy is implemented with the one-against-one Support Vector Machines Classifier (SVC), which is improved by employing a fault dictionary to accelerate the testing procedure. In our investigations, the support vectors and other relevant parameters are obtained by training the standard binary support vector machines. In addition, a technique of radial-basis-function (RBF) kernel parameter evaluation and selection is invented. This technique can find a good and proper kernel parameter for the SVC prior to the machine learning. Two typical analog circuits are demonstrated to validate the effectiveness of the proposed method.
This paper provides an overview of the effects of timing jitter in audio sampling analog-to-digital converters (ADCs), i.e. PCM (conventional or Nyquist sampling) ADCs and sigma-delta (ΣΔ) ADCs. Jitter in a digital audio is often defined as short-term fluctuations of the sampling instants of a digital signal from their ideal positions in time. The influence of the jitter increases particularly with the improvements in both resolution and sampling rate of today's audio ADCs. At higher frequencies of the input signals the sampling jitter becomes a dominant factor in limiting the ADCs performance in terms of signal-to-noise ratio (SNR) and dynamic range (DR).