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Abstract

High-speed serial standards are rapidly developing, and with a requirement for effective compliance and characterization measurement methods. Jitter decomposition consists in troubleshooting steps based on jitter components from decomposition results. In order to verify algorithms with different deterministic jitter (DJ) in actual circuits, jitter generation model by cross-point calibration and timing modulation for jitter decomposition is presented in this paper. The generated jitter is pre-processed by cross-point calibration which improves the accuracy of jitter generation. Precisely controllable DJ and random jitter (RJ) are generated by timing modulation such as data-dependent jitter (DDJ), duty cycle distortion (DCD), bounded uncorrelated jitter (BUJ), and period jitter (PJ). The benefit of the cross-point calibration was verified by comparing generation of controllable jitter with and without cross-point calibration. The accuracy and advantage of the proposed method were demonstrated by comparing with the method of jitter generation by analog modulation. Then, the validity of the proposed method was demonstrated by hardware experiments where the jitter frequency had an accuracy of 20 ppm, the jitter amplitude ranged from 10 ps to 8.33 ns, a step of 2 ps or 10 ps, and jitter amplitude was independent of jitter frequency and data rate.
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Authors and Affiliations

Nan Ren
1
Zaiming Fu
1
Shengcun Lei
1
Hanglin Liu
1
Shulin Tian
1

  1. University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China
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Abstract

Adjustable-width pulse signals are widely used in systems such as test equipment for hold time, response time and radar testing. In this study, we proposed a pulse generation method based on virtual sampling with ultra-high pulse width resolution. In the proposed method, the sampling rate of a digital-to-analogue converter (DAC) was adjusted to considerably improve pulse width resolution. First, the sampling rate was matched with the target pulse width resolution to digitally sample the ideal signal and generate digital waveform sampling points. Next, the signal bandwidth of the DAC was matched using a low-pass digital filter. Finally, the waveform sampling points were downsampled using an integer factor and output after digital-to-analogue conversion. The waveform pulse width information generated by high-frequency digital sampling was passed step by step and retained in the final output analogue signal. A DAC with a sampling rate of 1.25 GSa/s was used, and the pulse width resolution of the pulse signal was 0.1 ns. Theoretically, a sampling rate of 10 GSa/s is required to achieve 0.1 ns resolution. This method is simple, has a low cost, and exhibits excellent performance.
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Authors and Affiliations

Hanglin Liu
1
Zaiming Fu
1
Dexuan Kong
1
Houjun Wang
1
Yindong Xiao
1

  1. University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

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