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Abstract

This elaboration presents the concept of a unidirectional DC–DC switchedcapacitor converter operating as a voltage tripler. The system consists of two resonant cells with switched capacitors and chokes. This proposed converter topology achieves low voltages on semiconductor switches (diodes and transistors) compared to the classic SC series-parallel converter or the boost topology. The output voltage on the capacitors is reduced in the proposed converter because it is divided into two series-connected capacitors with asymmetric distribution. The presented results describe the analytical description of the system operation and the analytical equation for semiconductor currents. A simulation and experimental results have been performed. The system efficiency and three voltage gain values were measured in the experimental setup. The efficiency measured was also compared with the analytical determination curve for loss analysis and further converter optimization.
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Authors and Affiliations

Maciej Chojowski
1
Robert Sosnowski
1
Marcin Baszyński
1

  1. AGH University of Science and Technology, Poland
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Abstract

Adjustable-width pulse signals are widely used in systems such as test equipment for hold time, response time and radar testing. In this study, we proposed a pulse generation method based on virtual sampling with ultra-high pulse width resolution. In the proposed method, the sampling rate of a digital-to-analogue converter (DAC) was adjusted to considerably improve pulse width resolution. First, the sampling rate was matched with the target pulse width resolution to digitally sample the ideal signal and generate digital waveform sampling points. Next, the signal bandwidth of the DAC was matched using a low-pass digital filter. Finally, the waveform sampling points were downsampled using an integer factor and output after digital-to-analogue conversion. The waveform pulse width information generated by high-frequency digital sampling was passed step by step and retained in the final output analogue signal. A DAC with a sampling rate of 1.25 GSa/s was used, and the pulse width resolution of the pulse signal was 0.1 ns. Theoretically, a sampling rate of 10 GSa/s is required to achieve 0.1 ns resolution. This method is simple, has a low cost, and exhibits excellent performance.
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Authors and Affiliations

Hanglin Liu
1
Zaiming Fu
1
Dexuan Kong
1
Houjun Wang
1
Yindong Xiao
1

  1. University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu 611731, China

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