Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 3
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

Culture gas atmosphere is one of the most important factors affecting embryo development in vitro. The main objective of this study was to compare the effects of CO concentration on the subsequent pre-implantation developmental capacity of pig embryos in vitro, including embryos obtained via parthenogenesis, in vitro fertilization (IVF), and intracytoplasmic sperm injection (ICSI). Pig embryos were developed in four different CO2 concentrations in air: 3%, 5%, 10%, or 15%. The cleavage rate of pig parthenogenetic, IVF, or ICSI embryos developed in CO2 concen- trations under 5% was the highest. There were no significant differences in the oocyte cleavage rate in ICSI embryos in CO2 concentrations under 3% and 5% (p>0.05). However, as CO2 levels increased (up to 15%) the blastocyst output on day 7, from parthenogenetic, IVF, and ICSI em- bryos, decreased to 0%. These findings demonstrate that CO2 positively affects the developmen- tal capacity of pig embryos. However, high or low CO2 levels do not significantly improve the developmental capacity of pig embryos. The best results were obtained for all of the pig embryos at a 5% CO2 concentration.

Go to article

Authors and Affiliations

L. Zhang
Z. Lin
Y. Bi
X. Zheng
H. Xiao
Z. Hua
Download PDF Download RIS Download Bibtex

Abstract

This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog- AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
Go to article

Bibliography

[1] N. Arora, “MOSFET Modeling for VLSl Circuit Simulation: Theory and Practice,” World Scientific, 1993.
[2] International Technology Roadmap for Semiconductors. Available: http://www.itrs2.net, 2017.
[3] O. Samy, H. Abdelhamid, Y. Ismail, A. Zekry, “A 2D compact model for lightly doped DGMOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs),” Microelectronics reliability, 2016, 67, 82-88.
[4] J-P. Colinge, “FinFETs and Other Multi-Gate Transistors,” Springer, 2008.
[5] A. Amara, “Planar Double-Gate Transistor, From Technology to Circuit,” Springer, 2009.
[6] D. Stefanović, M. Kayal, M, “Structured Analog CMOS Design,” Springer, 2008.
[7] A. Mangla, M.-A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectronics journal, 2013, 44, 570-575.
[8] A.B. Bhattacharyya, “Compact MOSFET models for VLSI design,” Wiley, 2009.
[9] B. Smaani, S. Latreche, B. Iñiguez, „Compact drain-current model for undoped cylindrical surrounding-gate MOSFETs including short channel effects,” J. Appl. Phys., 2013, 114.
[10] J-M. Sallese, F. Krummenacher, F. Prégaldiny, „A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism,” Solid-State Electronics, 2012, 49, 485-489.
[11] O. Moldovan, F. Lime, S. Barraud, B. Smaani, „Experimentally verified drain-current model for variable barrier transistor,” IET Electronics Letters, 2015, 51, 17, 364–366.
[12] J. Alvarado, B. Iñiguez, M. Estrada, “Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation,” Int. J. Numer. Model, 2010, 23, 88–106.
[13] O. Cobianu, M. Soffke, A. Glesner, “Verilog-A model of an undoped symmetric dual-gate MOSFET,” Int. Adv. Radio Sci, 2006, 4, 303–306.
[14] M. Cheralathan, E. Contreras, J. Alvarado, “Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models,” Microelectronics Journal, 2013, 44, 80–85. [15] Verilog-AMS User Manual, Accellera 2006.
[16] B. Smaani, M. Bella, S. Latreche, “Compact Modeling of Lightly Doped Nanoscale DG MOSFET Transistor,” Applied Mechanics and Materials, 2014, 492, 06–10.
[17] O. Samy, H. Abdelhamid , Y. Ismail, A. Zekry, “A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs),” Microelectronics Reliability, 2016, 67, 82-88.
[18] Y. Taur, X. Liang, “A continuous, analytic drain-current model for DG MOSFETs,” IEEE Electron device Letters, 2004, 25, 2, 107–109.
[19] J-M. Sallese, A. S. Porret, “A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation,” Solid-State Electronics, 2000, 44, 887-894.
[20] H. Børli, S. Kolberg, “Capacitance modeling of short-channel double-gate MOSFETs,” Solid-State Electronics, 2008, 52, 1486–1490.
[21] C. Enz, F. Krummenacher, A.Vittoz, “An analytical MOS Transistor Model Valid in All Regions of Operation Dedicated to low voltage and low current applications,” Analog and integrated Circuits and Signal Processing, 1995, 8, 83-114.
[22] M. Bella, S. Latreche, C. Gontrand, “Nanoscale DGMOSFET: DC modification and Analysis of Noise in RF Oscillator,” Journal of Applied Sciences,2015, 5, 800–807.
[23] R. Blaise, W. Tekam, J. Kengne, G. D. Kenmoe, “High frequency Colpitts’ oscillator: A simple configuration for chaos generation,” Chaos, Solitons & Fractals, 2019, 126, 351–360.
[24] A.Rana1, P. Gaikwad, “Colpitts oscillator: design and performance optimization,” Int. Journal of Applied Sciences and Engineering Research, 2014, 3, 913–919.
[25] SMASH User Manual Version 5.18 Release, 2012.
[26] Device simulator ATLAS, Silvaco International, 2007.
Go to article

Authors and Affiliations

Billel Smaani
1
Yacin Meraihi
2
Fares Nafa
2
Mohamed Salah Benlatreche
3
Hamza Akroum
4
Saida Latreche
5

  1. Ingénierie des Systémes Electriques Department, Faculty of Technology, Boumerdes University, Algeria
  2. Laboratoire d'Ingénierie et Systèmes de Télécommunications, Faculté de Technologie, Boumerdes, Algeria
  3. Centre Universitaire Abdel Hafid Boussouf Mila, Algeria
  4. Laboratoire d’Automatique Appliquée, Université M’Hamed Bougara de Boumerdes, Algeria
  5. Laboratoire Hyperfréquences et Semiconducteurs, Electronique Department, Constantine 1 University, Algeria
Download PDF Download RIS Download Bibtex

Abstract

In this study, lead-free 0.94 Na0.5Bi0.5TiO3-0.06BaTiO3 (NBT-BT) compositions at morphotropic phase boundary were successfully synthesized by solid-state reaction method. The effects of the particle size for various milling time (12-24-48 hours) and sintering temperatures (1100-1125-1150-1175oC for 2h) on the electrical properties of the NBT-BT ceramics were evaluated. Experimental results showed that particle size and sintering temperatures significantly affect the electrical properties of NBT-BT ceramics. The particle size of the ceramic powders decreasing while milling time increases to 48 hours. Particle size values for 0, 12, 24 and 48 hours (h) milled powders were measured as nearly 1.5 µm, 1 µm, 700 nm, and 500 nm respectively. The bulk density enhanced with increasing sintering temperature and showed the highest value (5.73 g/cm3) at 1150oC for 48h milled powder. Similarly, the maximum piezoelectric constant (d33) = 105 pC/N, electromechanical coupling coefficient (kp) = 25.5% and dielectric constant (KT) = 575 were measured at 1150oC for 48 h milled powder. However, mechanical quality factor (Qm) was reduced from 350 to 175 with decreasing particle size. Similarly, remnant polarization was dropped by decreasing powder particle size from 56 μC/cm2 to 45 μC/cm2.

Go to article

Authors and Affiliations

Mert Gul
Mevlüt Gurbuz
Abdi B. Gokceyrek
Aysegül Toktaş
Taner Kavas
Aydin Dogan

This page uses 'cookies'. Learn more