The paper concerns the problem of state assignment for finite state machines (FSM), targeting at PAL-based CPLDs implementations. Presented in the paper approach is dedicated to state encoding of fast automata. The main idea is to determine the number of logic levels of the transition function before the state encoding process, and keep the constraints during the process. The number of implicants of every single transition function must be known while assigning states, so elements of two level minimization based on Primary and Secondary Merging Conditions are implemented in the algorithm. The method is based on code length extraction if necessary. In one of the most basic stages of the logic synthesis of sequential devices, the elements referring to constraints of PAL-based CPLDs are taken into account.

The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.