The proportional-integral-derivative (PID) controller is widely used in various industrial applications such as process control, motor drives, magnetic and optical memory, automotive, flight control and instrumentation. PID tuning refers to the generation of PID parameters (Kp, Ki, Kd) to obtain the optimum fitness value for any system. The determination of the PID parameters is essential for any system that relies on it to function in a stable mode. This paper proposes a method in designing a predictive PID controller system using particle swarm optimization (PSO) algorithm for direct current (DC) motor application. Extensive numerical simulations have been done using the Mathwork’s Matlab simulation environment. In order to gain full benefits from the PSO algorithm, the PSO parameters such as inertia weight, iteration number, acceleration constant and particle number need to be carefully adjusted and determined. Therefore, the first investigation of this study is to present a comparative analysis between two important PSO parameters; inertia weight and number of iteration, to assist the predictive PID controller design. Simulation results show that inertia weight of 0.9 and iteration number 100 provide a good fitness achievement with low overshoot and fast rise and settling time. Next, a comparison between the performance of the DC motor with PID-PSO, with PID of gain 1, and without PID were also discussed. From the analysis, it can be concluded that by tuning the PID parameters using PSO method, the best gain in performance may be found. Finally, when comparing between the PID-PSO and its counterpart, the PI-PSO, the PID-PSO controller gives better performance in terms of robustness, low overshoot (0.005%), low minimum rise time (0.2806 seconds) and low settling time (0.4326 seconds).

This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.