Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 12
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12/10/8/6 bit.
Go to article

Authors and Affiliations

Huma Tabassum
1
Krishna Prathik BV
1
Sujatha S Hiremath
1

  1. RV College of Engineering, India
Download PDF Download RIS Download Bibtex

Abstract

A new method of noise generation based on software implementation of a 7-bit LFSR based on a common polynomial PRBS7 using microcontrollers equipped with internal ADCs and DACs and a microcontroller noise generator structure are proposed in the paper. Two software applications implementing the method: written in ANSI C and based on the LUT technique and written in AVR Assembler are also proposed. In the method the ADC results are used to reseed the LFSR after its each full work cycle, what improves randomness of generated data, which results in a greater similarity of the generated random signal to white noise, what was confirmed by the results of experimental research. The noise generator uses only the internal devices of the microcontroller, hence the proposed solution does not introduce hardware redundancy to the system.

Go to article

Authors and Affiliations

Zbigniew Czaja
Michał Kowalewski
Download PDF Download RIS Download Bibtex

Abstract

An implemented impedance measuring instrument is described in this paper. The device uses a dsPIC (Digital Signal Peripheral Interface Controller) as a processing unit, and a DDS (Direct Digital Synthesizer) to stimulate the measurement circuit composed by the reference impedance and the unknown impedance. The voltages across the impedances are amplified by programmable gain instrumentation amplifiers and then digitized by analog to digital converters. The impedance is measured by applying a seven-parameter sine-fitting algorithm to estimate the sine signal parameters. The dsPIC communicates through RS-232 or USB with a computer, where the measurement results can be analyzed. The device also has an LCD to display the measurement results.

Go to article

Authors and Affiliations

José Santos
Pedro Ramos
Download PDF Download RIS Download Bibtex

Abstract

In the paper a new implementation of a compact smart resistive sensor based on a microcontroller with internal ADCs is proposed and analysed. The solution is based only on a (already existing in the system) microcontroller and a simple sensor interface circuit working as a voltage divider consisting of a reference resistor and a resistive sensor connected in parallel with an interference suppression capacitor. The measurement method is based on stimulation of the sensor interface circuit by a single square voltage pulse and on sampling the resulting voltage on the resistive sensor. The proposed solution is illustrated by a complete application of the compact smart resistive sensor used for temperature measurements, based on an 8-bit ATxmega32A4 microcontroller with a 12-bit ADC and a Pt100 resistive sensor. The results of experimental research confirm that the compact smart resistive sensor has 1°C resolution of temperature measurement for the whole range of changes of measured temperatures.

Go to article

Authors and Affiliations

Zbigniew Czaja
Download PDF Download RIS Download Bibtex

Abstract

This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
Go to article

Authors and Affiliations

D. S. Shylu Sam
1
P. Sam Paul
1
Diana Jeba Jingle
2
P. Mano Paul
3
Judith Samuel
1
J. Reshma
1
P. Sarah Sudeepa
1
G. Evangeline
1

  1. Karunya Institute of Technology & Sciences, Coimbatore, India
  2. Christ (Deemed to be University), Bangalore, India
  3. Alliance University, Bangalore, India
Download PDF Download RIS Download Bibtex

Abstract

The Sinara hardware platform is a modular, opensource measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and submicrosecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics.
Go to article

Authors and Affiliations

Grzegorz Kasprowicz
1
Thomas Harty
2
Sébastien Bourdeauducq
3
Robert Jördens
4
David Allcock
5
Daniel Slichter
6
David Nadlinger
2
Joseph W. Britton
7 8
Ana Sotirova
2

  1. Warsaw University of Technology, Poland
  2. Oxford University, United Kingdom
  3. M-Labs, Hong Kong
  4. QUARTIQ, Germany
  5. Oregon University, United States
  6. National Institute of Standards and Technology (NIST), United States
  7. University of Maryland, United States
  8. Army Research Lab, United States
Download PDF Download RIS Download Bibtex

Abstract

In this paper, aluminium alloy of grade ADC-12 was considered as a base metal and chromium carbide (Cr3C2) particles were reinforced through friction stir process. A detailed analysis of mechanical property and metallurgical characterization studies were performed to evaluate the surface composite. Remarkable changes were observed in the developed composite due to the mechanical force produced by the stir tool with an increase in hardness. The metallurgical investigation infers that the presence of silica in ADC-12 alloys has undergone mechanical fracture and long needle structure changed to reduced size. On the other hand, at higher tool rotational speed, the uniform distribution of hard particles was confirmed through SEM micrographs. Thus the modified surface composite has produced good mechanical property with high metallurgical qualities.

Go to article

Authors and Affiliations

J. Satheeshkumar
M. Jayaraman
G. Suganya Priyadharshini
ORCID: ORCID
C.S. Sathya Mukesh
Download PDF Download RIS Download Bibtex

Abstract

This paper provides an overview of the effects of timing jitter in audio sampling analog-to-digital converters (ADCs), i.e. PCM (conventional or Nyquist sampling) ADCs and sigma-delta (ΣΔ) ADCs. Jitter in a digital audio is often defined as short-term fluctuations of the sampling instants of a digital signal from their ideal positions in time. The influence of the jitter increases particularly with the improvements in both resolution and sampling rate of today's audio ADCs. At higher frequencies of the input signals the sampling jitter becomes a dominant factor in limiting the ADCs performance in terms of signal-to-noise ratio (SNR) and dynamic range (DR).

Go to article

Authors and Affiliations

Zbigniew Kulka
Download PDF Download RIS Download Bibtex

Abstract

NTC thermistors are frequently used low in cost temperature sensors which provide some of the most desirable sensing features. However, due to the nonlinear static transfer function their sensitivity decreases with temperature increase, causing lower measurement accuracy in some regions of the measurement range. This paper proposes a method for NTC thermistor nonlinearity compensation using a Wheatstone bridge and a novel dual-stage single-flash piecewise-linear ADC. Both conversion stages are performed using the same flash ADC of a novel design based on a reduced number of comparators employed. In this manner, simpler design, lower production costs, higher compactness and lower power consumption of the linearizing ADC, are achieved. The proposed linearizing method is tested on the Vishay NTCLE413E2103F520L thermistor, in the range from 0°C to 100°C, and the obtained results confirmed the effectiveness of the method in measurement accuracy improvement: when the flash ADC of 10-bit resolution is employed the accuracy obtained is 7:4747 10-5°C.
Go to article

Bibliography

[1] Michalski, L., Eckersdorf, K., Kucharski, J., & McGhee, J. (2001). Temperature Measurement. John Wiley & Sons, Ltd. https://doi.org/10.1002/0470846135
[2] Webster, J., & Eren, H. (2014). Measurement, Instrumentation, and Sensors Handbook: Spatial, Mechanical, Thermal, and Radiation Measurement. CRC Press. https://doi.org/10.1201/b15474
[3] Vishay. (2020). NTC Thermistors, Mini Epoxy PVC Twin Insulated Leads. [Datasheet NTCLE413, Document Number: 29078]. https://www.vishay.com/docs/29078/ntcle413.pdf
[4] Jeong, D. H., Kim, J. D., Song, H. J., Kim, Y. S., & Park, C. Y. (2015). Efficient calibration tool for thermistor temperature measurements. Applied Mechanics and Materials, 764–765, 1304–1308. https://doi.org/10.4028/www.scientific.net/amm.764-765.1304
[5] Webster, J. G. (1999). The Measurement, Instrumentation and Sensors Handbook. CRC Press LLC. https://doi.org/10.1201/9781003040019
[6] Stankovic, S. B., & Kyriacou, P. A. (2011). Comparison of thermistor linearization techniques for accurate temperature measurement in phase change materials. Journal of Physics: Conference Series. 307(1), 1–6. https://doi.org/10.1088/1742-6596/307/1/012009
[7] Lukic, J., & Denic, D. (2015). A novel design of an NTC thermistor linearization circuit. Metrology and Measurement Systems, 22(3), 351–362. https://doi.org/10.1515/mms-2015-0035
[8] Oladimeji, I., Sabo Miya, H., Abdulkarim, A., Mudathir, A., & Amuda, S. (2019). Design of Wheatstone bridge based thermistor signal conditioning circuit for temperature measurement. Journal of Engineering Science and Technology Review. 12(1), 12–17. https://doi.org/10.25103/jestr.121.02
[9] Nagarajan, P. R., George, B., & Kumar, V. J. (2017). A linearizing digitizer for Wheatstone bridge based signal conditioning of resistive sensors. IEEE Sensors Journal, 17(6), 1696–1705. https://doi.org/10.1109/JSEN.2017.2653227
[10] Nenova, Z., & Nenov T. (2009). Linearization circuit of the thermistor connection. IEEE Transactions on Instrumentation and Measurement, 58(2), 441–449. https://doi.org/10.1109/TIM.2008.2003320
[11] Maiti, T. (2008). A new hardware approach for the linearization of remote thermistor temperaturevoltage characteristic. International Journal of Electronics, 95(2), 169–176. https://doi.org/10.1080/00207210801915642
[12] Sarkar, A., Dey, D., & Munshi, S. (2013). Linearization of NTC thermistor characteristic using opamp based inverting amplifier. IEEE Sensors Journal, 13(12), 4621–4626. https://doi.org/10.1109/JSEN.2013.2267332
[13] Lopez-Martin, A. J., & Carlosena, A. (2013). Sensor signal linearization techniques: A comparative analysis. Proceedings of the IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), Peru, 1–4. https://doi.org/10.1109/LASCAS.2013.6519013
[14] Dias Pereira, J. M., Postolache, O., & Silva Girao, P. M. B. (2007). A digitally programmable A/D converter for smart sensors applications. IEEE Transactions on Instrumentation and Measurement, 56(1), 158–163. https://doi.org/10.1109/TIM.2006.887771
[15] Santos, M., Horta, N., & Guilherme, J. (2014). A survey on nonlinear analog-to-digital converters. Integration, the VLSI Journal, 47(1), 12–22. https://doi.org/10.1016/j.vlsi.2013.06.001
[16] Mohan, N. M., Kumar, V. J., & Sankaran, P. (2011). Linearizing dual-slope digital converter suitable for a thermistor. IEEE Transactions on Instrumentation and Measurement, 60(5), 1515–1521. https://doi.org/10.1109/TIM.2010.2092875
[17] Mahaseth, D., Kumar, L., & Islam, T. (2018). An efficient signal conditioning circuit to piecewise linearizing the response characteristic of highly nonlinear sensors. Sensors and Actuators A: Physical, 280(2018), 559–572. https://doi.org/10.1016/j.sna.2018.08.001
[18] Lukic, J., Živanovic, D.,&Denic, D. (2015). A compact and cost-effective linearization circuit used for angular position sensors. Facta Universitatis Series: Automatic Control and Robotics, 14(2), 123–134.
[19] Lopez-Martin, A. J., Zuza, M., & Carlosena, A. (2003). A CMOS A/D converter with piecewise linear characteristic and its application to sensor linearization. Analog Integrated Circuits and Signal Processing, 36(1–2), 39–46. https://doi.org/10.1023/A:1024437311497
[20] Bucci, G., Faccio, M., & Landi, C. (2000). New ADC with piecewise linear characteristic: case studyimplementation of a smart humidity sensor. IEEE Transactions on Instrumentation and Measurement, 49(6), 1154–1166. https://doi.org/10.1109/19.893250
[21] Chio, U. F.,Wei, H. G., Zhu, Y., Sin, S. W., U. S. P., Martins, R. P.,&Maloberti, F. (2010). Design and experimental verification of a power effective flash-SAR subranging ADC. IEEE Transactions on Circuits and Systems – II: Express Briefs, 57(8), 607–611. https://doi.org/10.1109/TCSII.2010.2050937
[22] Jovanovic, J., & Denic, D. (2016). A cost-effective method for resolution increase of the two-stage piecewise linear ADC used for sensor linearization. Measurement Science Review, 16(1), 28–34. https://doi.org/10.1515/msr-2016-0005
[23] Lee, J. I., & Song, J. (2013). Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count. Proceedings of the IEEE International Conference of IEEE Region 10 (TENCON 2013), China, 1–4. https://doi.org/10.1109/TENCON.2013.6718487
[24] Lee,W., Huang, P., Liao,Y.,&Hwang,Y. (2007).Anewlowpower flashADCusing multiple-selection method. Proceedings of the IEEE Conference on Electron Devices and Solid-State Circuits, Taiwan, 341–344. https://doi.org/10.1109/EDSSC.2007.4450132
[25] International Electrotechnical Commission. (2015). Preferred number series for resistors and capacitors (IEC 60063:2015). https://webstore.iec.ch/publication/22011
[26] Fraden, J. (2010). Handbook of Modern Sensors: Physics, Designs, and Applications. Springer Science + Business Media. https://doi.org/10.1007/978-1-4419-6466-3
[27] Regtien, P., & Dertien, E. (2018). Sensors for Mechatronics. Elsevier. https://doi.org/10.1016/ C2016-0-05059-3
Go to article

Authors and Affiliations

Jelena Jovanović
1
Dragan Denić
1

  1. University of Niš, Faculty of Electronic Engineering, Measurements Department, Aleksandra Medvedeva 14, 18000 Niš, Serbia
Download PDF Download RIS Download Bibtex

Abstract

The paper is a review of analog and digital electronics dedicated to monitor nanosecond pulses. Choosing the optimal peak detector construction depends on many factors for example precision, complexity, or costs. The work shows some virtues and limitations of selected peak detection methods, for example standard peak detector with rectifier, sample and hold circuit with triggering units and ADC fast acquisition. However, the main attention is paid to problems of results from effective triggering signal for sample and hold operation. The obtained results allow for designing a peak detector construction as an alternative for costly and very complex fast acquisition systems based on ADC and FPGA technologies.

Go to article

Authors and Affiliations

Krzysztof Achtenberg
ORCID: ORCID
Janusz Mikołajczyk
ORCID: ORCID
Dariusz Szabra
Artur Prokopiuk
Zbigniew Bielecki
ORCID: ORCID
Download PDF Download RIS Download Bibtex

Abstract

The development of digital microphones and loudspeakers adds new and interesting possibilities of their applications in different fields, extended from industrial, medical to consumer audio markets. One of the rapidly growing field of applications is mobile multimedia, such as mobile phones, digital cameras, laptop and desktop PCs, etc. The advances have also been made in digital audio, particularly in direct digital transduction, so it is now possible to create the all-digital audio recording and reproduction chains potentially having several advantages over existing analog systems.

Go to article

Authors and Affiliations

Zbigniew Kulka
Download PDF Download RIS Download Bibtex

Abstract

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 megasamples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Go to article

Bibliography

[1] Y. Zhou, B. Xu and Y. Chiu, “A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC,” IEEE Journal of Solid-State Circuits 54, 8, 2207-2218, (2019). https://doi.org/10.1109/JSSC.2019.2915583.
[2] D. Oh, J. Kim, D. Jo, W. Kim, D. Chang and S. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” IEEE Journal of Solid-State Circuits 54, 1, 288- 297,(2019). https://doi.org/10.1109/JSSC.2018.2870554.
[3] A. Wu, J. Wu, and J. Huang, “Energy-efficient switching scheme for ultra-low voltage SAR ADC.”, Analog Integr Circ Sig Process 90, 507–511, (2017). https://doi.org/10.1007/s10470-016-0892-0
[4] M. Guo, J. Mao, S. Sin, H. Wei and R. P. Martins, “A 1.6- GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration,”IEEE Journal of Solid-State Circuits 55, 3,693-705, (2020). https://doi.org/10.1109/JSSC.2019.2945298.
[5] M. Davidovic, G. Zach, H. Zimmermann, “An 11-bit successive approximation analog-to-digital converter based on a combined capacitor-resistor network.”, Elektrotech. Inftech. 127, 98–102, (2010). https://doi.org/10.1007/s00502-010-0704-7
[6] D. Chang, W. Kim, M. Seo, H. Hong, and S. Ryu, “Normalized- Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.”, IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, 322-332 (2017). https://doi.org/10.1109/TCSI.2016.2612692
[7] M. Shim et al.,“Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC”, IEEE Journal of Solid-State Circuits 52, 4, 1077-1090, (2017). https://doi.org/10.1109/JSSC.2016.2631299
[8] D. Zhang and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs 63, 3, 244-248, (2016). https://doi.org/10.1109/TCSII.2015.2482618.
[9] S.A. Zahrai, M. Onabajo, “ Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power- Efficient Hybrid Data Converters.”, J. Low Power Electron. Appl. 8, 12, (2018). https://doi.org/10.3390/jlpea8020012
[10] S.Taheri, J. Lin, J. S. Yuan,“Security Interrogation and Defense for SAR Analog to Digital Converter.”, Electronics 6, 48, (2017). https://doi.org/10.3390/electronics6020048
[11] J. Kim, B. Sung, W. Kim and S. Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS”, IEEE Journal of Solid-State Circuits 48, 6, 1429-1441, (2013). https://doi.org/10.1109/JSSC.2013.2252516
[12] S. Danesh, J. Hurwitz, K. Findlater, D. Renshaw and R. Henderson, “A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design”, IEEE Journal of Solid-State Circuits 48, 3, 733-748, (2013). https://doi.org/10.1109/JSSC.2013.2237672
[13] L. Wang, M. LaCroix and A. C. Carusone, “A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.”, IEEE Transactions on Circuits and Systems II: Express Briefs 64, 12, 1367-1371, (2017). https://doi.org/10.1109/TCSII.2017.2726063
[14] F. M´arquez, et al., “A novel autozeroing technique for flash Analog-to-Digital converters.”, Integration 47, 1, 23-29, (2014). https://doi.org/10.1016/j.vlsi.2013.06.002
[15] Masumeh Damghanian, Seyed Javad Azhari, “A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications.”, Integration 57, 158-168, (2017). https://doi.org/10.1016/j.vlsi.2017.01.006
[16] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan and J. J. Liou, “A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage,” IEEE Access 7, 93396- 93403,(2019). https://doi.org/10.1109/ACCESS.2019.2927514.
[17] A. Khatak, M. Kumar, S. Dhull, “An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits.”, J. Low Power Electron. Appl. 8, 33, (2018). https://doi.org/10.3390/jlpea8040033.
[18] B. Hershberg et al., “3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA 68-70, (2019). https://doi.org/10.1109/ISSCC.2019.8662319.
[19] U. Chio et al., “Design and Experimental Verification of a Power Effective Flash-SAR Sub ranging ADC.”, IEEE Transactions on Circuits and Systems II: Express Briefs 57, 8, 607-611, (2010). https://doi.org/10.1109/TCSII.2010.2050937
[20] Young-Deuk Jeon et al., “A dual-channel pipelined ADC with sub-ADC based on flash-SAR architecture.”, Circuits and Systems II: Express Briefs 59, 741-745. (2012). https://doi.org/10.1109/TCSII.2012.2222837
[21] Y. Lin et al.,“ A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.”, IEEE Transactions on Circuits and Systems I: Regular Papers 60, 3, 570-581, (2013). https://doi.org/10.1109/TCSI.2012.2215756
[22] J.I. Lee, J. Song, “Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count.”, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) 1-4, (2013). https://doi.org/10.1109/TENCON.2013.6718487
[23] A. Esmailiyan, F. Schembari and R. B. Staszewski, “A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump- Based Comparators in 28-nm CMOS,”IEEE Transactions on Circuits and Systems I: Regular Papers 67, 6, 1789-1802, (2020). https://doi.org/10.1109/TCSI.2020.2969804.
[24] J. Xu, et al., “Low-leakage analog switches for low-speed sample-and-hold circuits”, Microelectronics Journal 76, 22–27, (2018). https://doi.org/10.1016/j.mejo.2018.04.008
[25] M. Nazari, L. Sharifi,A. Aghajani, and O. Hashemipour, “A 12-bit high performance current-steering DAC using a new binary to thermometer decoder.”, 2016 24 Iranian Conference on Electrical Engineering (ICEE), Shiraz 2016 1919-1924, (2016). https://doi.org/10.1109/IranianCEE.2016.7585835
[26] H.S. Bindra et al., “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.”, IEEE Journal of Solid-State Circuits 53, 7, 1902-1912, (2018). https://doi.org/10.1109/JSSC.2018.2820147
[27] A. Taghizadeh, Z.D. Koozehkanani, J. Sobhi, “A new high-speed lowpower and low-offset dynamic comparator with a current-mode offset compensation technique.”, AEU - Int. J. Electron. Commun. 81, 163–170, (2018). https://doi.org/10.1016/j.aeue.2017.07.018.
[28] M. Saberi and R. Lotfi,“ Segmented Architecture for Successive Approximation Analog-to-Digital Converters.”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 3, 593-606, (2014). https://doi.org/10.1109/TVLSI.2013.2246592
[29] Y. Haga et al., “Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique.”, 2005 IEEE International Symposium on Circuits and Systems 1, 220-223, (2005). https://doi.org/10.1109/ISCAS.2005.1464564.
[30] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone- Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits 54, 3, 646-658, (2019). https://doi.org/10.1109/JSSC.2018.2889680.
[31] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC,” IEEE Journal of Solid-State Circuits 50, 12, 2901-2911, (2015). https://doi.org/10.1109/JSSC.2015.2463094
[32] B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.”, IEEE Communications Magazine 54, 4, 78-83, (2016). https://doi.org/10.1109/MCOM.2016.7452270
[33] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur196-199, (2010). https://doi.org/10.1109/APCCAS.2010.5774747.
[34] M. Hotta et al., “SAR ADC Architecture with Digital Error Correction.”. IEEJ Trans Elec Electron Eng 5, 651-659, (2010). https://doi.org/10.1002/tee.20588
[35] S. Lee, A.P. Chandrakasan and H. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC with Background Timing Skew Calibration.”, IEEE Journal of Solid-State Circuits 49, 12, 2846-2856, (2014). https://doi.org/10.1109/JSSC.2014.2362851
[36] M. Damghanian and S.J. Azhari, “A novel three-section encoder in a low-power 2.3 GS/s flash ADC.”, Microelectronics J 82, 71–80, (2018). https://doi.org/10.1016/j.mejo.2018.10.009
[37] Yi. Shen and Z. Zhu, “Analysis and optimization of the twostage pipelined SAR ADCs.”, Microelectronics Journal 47, 1–5, (2016). https://doi.org/10.1016/j.mejo.2015.10.018.
[38] Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu,“A 10-bit 100-MS/s 5.23 mW SAR ADC in 0.18 μm CMOS.”,Microelectronics Journal 78, 63-72, (2018). https://doi.org/10.1016/j.mejo.2018.06.007
[39] X. Xin et al.,“A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip.”,Microelectronics Journal 83, 104–116, (2019). https://doi.org/10.1016/j.mejo.2018.11.017
[40] W. Guo, S. Liu, and Z. Zhu, “ An asynchronous 12-bit 50MS/s rail-torail Pipeline-SAR ADC in 0.18 μm CMOS.”, Microelectronics Journal 52, 23–30, (2016). https://doi.org/10.1016/j.mejo.2016.03.003
[41] B. Samadpoor Rikan et al.,“A 10-bit 1 MS / s segmented Dual-Sampling SAR ADC with reduced switching energy.”, Microelectronics Journal 70, 89–96, (2017). https://doi.org/10.1016/j.mejo.2017.11.005
Go to article

Authors and Affiliations

Anil Khatak
1
ORCID: ORCID
Manoj Kumar
2
Sanjeev Dhull
3

  1. Faculty of Biomedical Engineering, GJUS&T, Hisar, Haryana, India
  2. Faculty of USICT, Guru Gobind Singh Indraprastha University, New Delhi, India
  3. Faculty of ECE, GJUS&T, Hisar, Haryana, India

This page uses 'cookies'. Learn more