In this paper, Recursive Least Square (RLS) and Affine Projection (AP) adaptive filters are designed using Xilinx System Generator and implemented on the Spartan6 xc6slx16- 2csg324 FPGA platform. FPGA platform utilizes the non-restoring division algorithm and the COordinate Rotation DIgital Computer (CORDIC) division algorithm to perform the division task of the RLS and AP adaptive filters. The Non-restoring division algorithm demonstrates efficient performance in terms of convergence speed and signal-to-noise ratio. In contrast, the CORDIC division algorithm requires 31 cycles for division initialization, whereas the non-restoring algorithm initializes division in just one cycle. To validate the effectiveness of the proposed filters, a set of ten ECG records from the BIT-MIT database is used to test their ability to remove Power Line Interference (PLI) noise from the ECG signal. The proposed adaptive filters are compared with various adaptive algorithms in terms of Signal-to-Noise Ratio (SNR), convergence speed, residual noise, steady-state Mean Square Error (MSE), and complexity.

In order to guarantee the accuracy of turntable angle measurement, a real-time compensation method for turntable positioning precision based on harmonic analysis is proposed in this paper. Firstly, the principle and feasibility of the real-time compensation method are analysed, and a detailed description of harmonic compensation is provided herein. Secondly, we analyse the relationships between the surface number of the polygon with the compensation order of the harmonic function and its corresponding compensation accuracy. The effects of the iterations number and the data width on calculation accuracy in the coordinate rotation digital computer (CORDIC) algorithm are analysed and the quantization models of the approximation error and rounding error of the CORDIC algorithm are established. Then, the calculation of the harmonic error function and real-time compensation processes are implemented on a field programmable gate array (FPGA) chip. The resource occupation and time delay of the phase angle calculation and the harmonic component calculation are discussed separately. Finally, the validity of the harmonic compensation method is proven through comparing the compensation effect with that of linear interpolation and the polynomial compensation method. The influences of the compensation order, the iterations number and the data width on the compensation results are demonstrated by simulation. A test platform with a laboratory-made FPGA circuit is built to evaluate the effect of real-time compensation with the harmonic function and the positioning error compensation can be performed within 760 ns. The results confirmed the effectiveness of the harmonic compensation method, revealing an improvement of the positioning precision from 54.21″ to 1.63″, equivalent to 96.99% reduction in positioning error.