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Measurement Capabilities Upgrade of GEM Soft X-ray Measurement System for Hot Plasma Diagnostics

Paweł Linczuk Andrzej Wojenski Piotr Kolasinski Rafał Krawczyk Wojciech Zabolotny Krzysztof Pozniak Maryna Chernyshova Tomasz Czarski Michał Gaska Grzegorz Kasprowicz Karol Malinowski
International Journal of Electronics and Telecommunications | 2021 | vol. 67 | No 1 | 115-120 | DOI: 10.24425/ijet.2021.135952
Keywords Measurement system GEM DAQ
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Abstract

The paper presents improvements of the developed system for hot plasma radiation measurement in the soft Xray range based on a Gas Electron Multiplier (GEM) detector. Scope of work consists of a new solution for handling hardware time-synchronization with tokamak systems needed for better synchronization with other diagnostics and measurement quality. The paper describes the support of new modes of triggering on PC-side. There are communication and data path overview in the system. The new API is described, which provide separate channels for data and control and is more robust than the earlier solution. Work concentrates on stability and usability improvements of the implemented device providing better usage for end-user.
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Authors and Affiliations

Paweł Linczuk
1
Andrzej Wojenski
2
Piotr Kolasinski
2
Rafał Krawczyk
2 3
Wojciech Zabolotny
2
Krzysztof Pozniak
2
Maryna Chernyshova
4
Tomasz Czarski
4
Michał Gaska
2
Grzegorz Kasprowicz
2
Karol Malinowski
4
  1. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  2. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  3. CERN, Geneva, Switzerland
  4. Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland

Zero-Suppression Trigger Mode for GEM Detector Measurement System

Piotr Kolasinski Krzysztof Pozniak Andrzej Wojenski Paweł Linczuk Rafał Krawczyk Michał Gaska Wojciech Zabolotny Grzegorz Kasprowicz Maryna Chernyshova Tomasz Czarski
International Journal of Electronics and Telecommunications | 2021 | vol. 67 | No 1 | 103-108 | DOI: 10.24425/ijet.2021.135950
Keywords FPGA GEM trigger sequencer DAQ Xilinx
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Abstract

A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.
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Authors and Affiliations

Piotr Kolasinski
1
Krzysztof Pozniak
1
Andrzej Wojenski
1
Paweł Linczuk
2
Rafał Krawczyk
1 3
Michał Gaska
1
Wojciech Zabolotny
1
Grzegorz Kasprowicz
1
Maryna Chernyshova
4
Tomasz Czarski
4
  1. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  2. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  3. CERN, Geneva, Switzerland
  4. Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland

SoPC-based DMA for PCI Express DAQ Cards

Krzysztof Mroczek
International Journal of Electronics and Telecommunications | 2021 | vol. 67 | No 4 | 565-570 | DOI: 10.24425/ijet.2021.137847
Keywords DAQ DMA SoC PCI Express FPGA transient analysis
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Abstract

This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including pre-triggering acquisition for transient analysis and multichannel transmission. Performance of the interface has been evaluated on Terasic OVSK board (PCIe Gen2 x4). Target configuration of this interface is based on the Avalon-MM Hard IP for Cyclone V PCIe core and Jungo WinDriver x64 for Windows. A sample speed of 1200 MB/s has been reported for DMA writes to PCIe memory.
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Bibliography

[1] PCI Express Base Specification, rev. 3.0, PCI-SIG, Nov. 2010
[2] A. Wójcik, R. Łukaszewski, R. Kowalik, W. Winiecki, “Nonintrusive Appliance Load Monitoring: An Overview, Laboratory Test Results and Research Directions”, Sensors, 2019, 19, 3621
[3] A. Wójcik, P. Bilski, R. Łukaszewski, K. Dowalla, R. Kowalik, “Identification of the State of Electrical Appliances with the Use of a Pulse Signal Generator”, Energies, 2021, 14, 673.
[4] K. N. Trung, E. Dekneuvel, B. Nicolle, O. Zammit, C. N. Van, G. Jacquemod, “Using FPGA for Real Time Power Monitoring in a NIALM System”, In Proc. 2013 IEEE International Symposium on Industrial Electronics (ISIE), 2013, pp. 1-6
[5] Intel Corporation, Modular Scatter-Gather DMA Core, In Embedded Peripherals IP User Guide v. 18.1
[6] Intel Corporation, Intel® Quartus® Prime Standard Edition User Guide v. 18.1, Platform Designer
[7] Intel Corporation, Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe Solutions User Guide, UG-01110, 2020
[8] Intel Corporation,V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide, UG-01154, 2016
[9] WinDriver, https://www.jungo.com/st/products/windriver/wd_windows/
[10] OpenVINO Stater Kit GT Edition User Manual, available on https://www.terasic.com.tw/
[11] L. Rota, M. Caselle, S. Chilingaryan, A. Kopmann, M. Weber, “A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission”, IEEE Transactions on Nuclear Science, vol. 62, no. 3, 2015, pp. 972 - 976
[12] A. Byszuk, J. Kołodziejski, G. Kasprowicz, K. Późniak, W. M. Zabołotny “Implementation of PCI Express bus communication for FPGA-based data acquisition systems”, In Proceedings of SPIE Vol. 8454, 2015
[13] L. Boyang, “Research and Implementation of XDMA High Speed Data Transmission IP Core Based on PCI Express and FPGA”, in 2019 IEEE 1st International Conference on Civil Aviation Safety and Information Technology (ICCASIT), Oct. 2019, pp. 408–411
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Authors and Affiliations

Krzysztof Mroczek
1
  1. Institute of Radioelectronics and Multimedia Technology, Warsaw University of Technology, Poland

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