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Abstract

High definition video transmission is one of the prime demands of modern day communication. Changing needs demand diverse features to be offered by the video codec standards, H.264 fits to these requirements for video compression. In this work, an attempt has been made to optimize the inter prediction along with improved intra prediction to ensure the minimal bit rates thereby reduction in the channel bandwidth, which is required in most of the wireless applications. In intraprediction, only DC prediction mode is chosen out of 9 modes with 4*4 luma blocks that reduces the coding complexity towards optimal logic utilization in order to support typical FPGA board for hardware implementation. Most significantly, Inter prediction is carried out utilizing the M9K blocks efficiently with proper timing synchronization to reduce the latency in the encoding operation. Experimental set up comprising of two Altera DE2-115 boards connected through Ethernet cable demonstrated the video transmission. These optimized intra prediction and inter prediction stages resulted in significant improvement in the video compression possessing good subjective quality and increased video compression.
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Bibliography

[1] Bernatin.T ,Sundari.G, “ Video compression based on Hybrid transform and quantization with Huffman coding for video codec”, International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), pp 476-480,IEEE.
[2] The Evolution of H.264 From Codec to System Architecture, White Paper , VBrick Systems, December, 2010
[3] Arun Kumar Pradhan, Lalit Kumar Kanoje and BiswaRanjan Swain, 2013 “FPGA based High Performance CAVLC Implementation for H.264 Video Coding” International Journal of Computer Applications (0975 – 8887) Volume 69– No.10.
[4] Teng Wang, Chih-Kuang Chen, Qi-Hua Yang and Xin-An Wang (2012), “FPGA Implementation and Verification System of H.264/AVC Encoder for HDTV Applications”, Advances in CSIE, Springer-Verlag Berlin Heidelberg, Vol. 2, AISC 169, pp. 345-352
[5] Gwo-Long Li et al. (2013), “135-MHz258-K gates VLSI design for all-intra H.264/AVC scalable video encoder”, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., Vol. 21, No. 4, pp. 636-647
[6] Kuo, H.-C., Wu, L.-C., Huang, H.-T., Hsu, S.-T. and Lin, Y.-L. (2013), “A low power high-performance H.264/AVC intra-frame encoder for 1080pHD video”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 19, No. 6, pp. 925-938

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Authors and Affiliations

T. Bernatin
1
G. Sundari
1
Sahaya Anselin Nisha
1
M.S. Godwin Premi
1

  1. Sathyabama Institute of Science and Technology, India
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Abstract

The continuous growth of smart communities and ever-increasing demand of sending or storing videos, have led to consumption of huge amount of data. The video compression techniques are solving this emerging challenge. However, H.264 standard can be considered most notable, and it has proven to meet problematic requirements. The authors present (BPMM) as a novel efficient Intra prediction scheme. We can say that the creation of our proposed technique was in a phased manner; it's emerged as a proposal and achieved impressive results in the performance parameters as compression ratios, bit rates, and PSNR. Then in the second stage, we solved the challenges of overcoming the obstacle of encoding bits overhead. In this research, we try to address the final phase of the (BPMM) codec and to introduce our approach in a global manner through realization of decoding mechanism. For evaluation of our scheme, we utilized VHDL as a platform. Final results have proven our success to pass bottleneck of this phase, since the decoded videos have the same PSNR that our encoder tells us, while preserving steady compression ratio treating the overhead. We aspire our BPMM algorithm will be adopted as reference design of H.264 in the ITU.

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Authors and Affiliations

Sara Hamdy
Abdelhalim Zekry
Wael A. Mohamed

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