Abstract
As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the ”spiral wiring” way and the ”double spiral wiring” way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs.
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Bibliography
[1] Gong Yonglin. The hot spots of printed circuit technology in 2020. Printed Circuit Information, 28(2):1–11, 2020.
[2] Myeonghoon Oh, Youngwoo Kim, Hag Young Kim, Young Kyun Kim, and Jinsung Kim. Wire optimization and delay reduction for highperformance on-chip interconnection in gals systems. Etri Journal, 39(4):582–591, 2017.
[3] YuanWei-Qun, Song Jian-Yuan, Chen Shi-Rong, Suntak Technology Co, and LTD. Research and optimization design of high-speed pcb based on signal integrity. Journal of Guangdong University of Technology, 36(6):74–79, 2019.
[4] L.W.; Zhao Z.L. Yang, C.Z.; De. Research on signal integrity in high speed digital pcb board design. Automation and Instrumentation, (9):1– 4, 2018.
[5] YuanWei-Qun, Song Jian-Yuan, Chen Shi-Rong, Suntak Technology Co, and LTD. Research and optimization design of high-speed pcb based on signal integrity. Journal of Guangdong University of Technology, 36(6):74–79, 2019.
[6] Zhang Min. Signal integrity and design optimization of high speed parallel bus interface. Wireless Internet Technology, 15(6):3–4, 2019.
[7] Nastaran Soleimani, Mohammad G H Alijani, and Mohammad Hassan Neshati. Crosstalk analysis of multi-microstrip coupled lines using transmission line modeling. International Journal of Rf and Microwave Computer-aided Engineering, 29(6), 2019.
[8] Y.; Wen C.L. Yong, J.H.; Ting. PADS software foundation and application examples. Publishing House of Electronics Industry, 2019.
[9] Teng Li. A study on si simulation of high-speed interconnection channel. Electronics and Packaging, 18(12):37–40, 2018.
[10] H. Sasaki, M. Kanazawa, T. Sudo, A. Tomishima, and T. Kaneko. New frequency dependent target impedance for ddr3 memory system. pages 1–4, 2011.
[11] C. Liao, B. Mutnury, C. Chen, and Y. Lee. Pcb stack-up design and optimization for next generation speeds. In 2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS), pages 155–158, 2016.
[12] Nastaran Soleimani, Mohammad GH Alijani, and Mohammad H Neshati. Crosstalk analysis at near-end and far-end of the coupled transmission lines based on eigenvector decomposition. AEU-International Journal of Electronics and Communications, 112:152944, 2019.
[13] X. Ye and C. Ye. Transmission lines and basic signal integrity. In 2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI PI), pages 1–51, 2018.
[14] Wang Xiaojing, Ye Ming, and Ma Yan. Research crosstalk between parallel interconnects. Electronic Measurement Technology, 2015.
[15] J. Fan, X. Ye, J. Kim, B. Archambeault, and A. Orlandi. Signal integrity design for high-speed digital circuits: Progress and directions. IEEE Transactions on Electromagnetic Compatibility, 52(2):392–400, 2010.
[16] Dong Zhang, L. I. Qiong, and Qianqin Qin. Application of simulation analysis based on ibis model to sdram pcb design. Journal of Wuhan University, 2011.
[17] A. K. Pandey. Power-aware signal integrity analysis of ddr4 data bus in onboard memory module. In 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), pages 1–4, 2016.
[18] Nastaran Soleimani, Mohammad GH Alijani, and Mohammad H Neshati. Crosstalk analysis of multi-microstrip coupled lines using transmission line modeling. International Journal of RF and Microwave Computer-Aided Engineering, 29(6):e21677, 2019.
[19] S. M¨uller, T. Reuschel, R. Rimolo-Donadio, Y. H. Kwark, H. Br¨uns, and C. Schuster. Energy-aware signal integrity analysis for high-speed pcb links. IEEE Transactions on Electromagnetic Compatibility, 57(5):1226– 1234, 2015.
[20] Jie Tang, Yi Gong, and Zhen Guo Yang. Failure analysis on cracking of blind and buried vias of printed circuit board for high-end mobile phones. Soldering and Surface Mount Technology, 31(4), 2019.
[21] Liu Lu, Cao Yuesheng, and Duo Ruihua. Design and realization of high-density fdr interconnection switch board. Computer Engineering, (6):3, 2016.
[22] M S Al Salameh and M M Ababneh. Selecting printed circuit board parameters using swarm intelligence to minimize crosstalk between adjacent tracks. International Journal of Numerical Modelling-electronic Networks Devices and Fields, 28(1):21–32, 2015.
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