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Abstract

A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.
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Authors and Affiliations

Piotr Kolasinski
1
Krzysztof Pozniak
1
Andrzej Wojenski
1
Paweł Linczuk
2
Rafał Krawczyk
1 3
Michał Gaska
1
Wojciech Zabolotny
1
Grzegorz Kasprowicz
1
Maryna Chernyshova
4
Tomasz Czarski
4

  1. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  2. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  3. CERN, Geneva, Switzerland
  4. Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland
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Abstract

In the past it was usual to exert a huge effort in the design, simulation, and the real time implementation of the complicated electronic and communication systems, like GNSS receivers. The complexity of the system algorithms combined with the complexity of the available tools created a system that is difficult to track down for debugging or for redesign. So, the simulation and educational tools was different from the prototyping tools. In this paper the parallel search acquisition phase of a GPS receiver was simulated and implemented on FPGA using the same platform and through a graphical programming language. So this paper introduces the fruit of integrating the prototyping tools with the simulation tools as a single platform through which the complicated electronic systems can be simulated and prototyped.

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Authors and Affiliations

Mohamed Ibrahiem El Hawary
Gihan Gomah Hamza
Abdelhalim Zekry
Ibrahiem Mohamed Motawie

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