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Number of results: 12
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Abstract

Field programmable analog arrays (FPAA), thanks to their flexibility and reconfigurability, give the designers quite new possibilities in analog circuit design. The number of both academic projects on FPAA and applications of commercially available programmable devices is still growing. This paper explores the properties and parameters of two most popular FPAA circuits: the AnadigmVortex AN221E04 and AnadigmApex AN231E04 from the Anadigm company. The research conducted by the authors led to the discovery of some undocumented features of these devices. Several applications for audio processing were built and tested. The results show that these circuits can be used in medium-demanding audio applications. Thanks to dynamic reconfigurability, they also allow to build an universal analog audio signal processor. These circuits can also act as a versatile platform for rapid prototyping and educational purposes.

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Authors and Affiliations

Piotr Falkowski
Andrzej Malcher
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Abstract

This paper is devoted to multiple soft fault diagnosis of analog nonlinear circuits. A two-stage algorithm is offered enabling us to locate the faulty circuit components and evaluate their values, considering the component tolerances. At first a preliminary diagnostic procedure is performed, under the assumption that the non-faulty components have nominal values, leading to approximate and tentative results. Then, they are corrected, taking into account the fact that the non-faulty components can assume arbitrary values within their tolerance ranges. This stage of the algorithm is carried out using the linear programming method. As a result some ranges are obtained including possible values of the faulty components. The proposed approach is illustrated with two numerical examples.

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Authors and Affiliations

Michał Tadeusiewicz
Stanisław Hałgas
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Abstract

The paper deals with fault diagnosis of nonlinear analogue integrated circuits. Soft spot short defects are analysed taking into account variations of the circuit parameters due to physical imperfections as well as self-heating of the chip. A method enabling to detect, locate and estimate the value of a spot defect has been developed. For this purpose an appropriate objective function was minimized using an optimization procedure based on the Fibonacci method. The proposed approach exploits DC measurements in the test phase, performed at a limited number of accessible points. For illustration three numerical examples are given.

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Authors and Affiliations

Michał Tadeusiewicz
Stanisław Hałgas
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Abstract

This paper deals with multiple soft fault diagnosis of nonlinear analog circuits comprising bipolar transistors characterized by the Ebers-Moll model. Resistances of the circuit and beta forward factor of a transistor are considered as potentially faulty parameters. The proposed diagnostic method exploits a strongly nonlinear set of algebraic type equations, which may possess multiple solutions, and is capable of finding different sets of the parameters values which meet the diagnostic test. The equations are written on the basis of node analysis and include DC voltages measured at accessible nodes, as well as some measured currents. The unknown variables are node voltages and the parameters which are considered as potentially faulty. The number of these parameters is larger than the number of the accessible nodes. To solve the set of equations the block relaxation method is used with different assignments of the variables to the blocks. Next, the solutions are corrected using the Newton-Raphson algorithm. As a result, one or more sets of the parameters values which satisfy the diagnostic test are obtained. The proposed approach is illustrated with a numerical example.

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Authors and Affiliations

Michał Tadeusiewicz
Stanisław Hałgas
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Abstract

The paper deals with a multiple fault diagnosis of DC transistor circuits with limited accessible terminals for measurements. An algorithm for identifying faulty elements and evaluating their parameters is proposed. The method belongs to the category of simulation before test methods. The dictionary is generated on the basis of the families of characteristics expressing voltages at test nodes in terms of circuit parameters. To build the fault dictionary the n-dimensional surfaces are approximated by means of section-wise piecewise-linear functions (SPLF). The faulty parameters are identified using the patterns stored in the fault dictionary, the measured voltages at the test nodes and simple computations. The approach is described in detail for a double and triple fault diagnosis. Two numerical examples illustrate the proposed method.

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Authors and Affiliations

S. Hałgas
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Abstract

Analog circuits need more effective fault diagnosis methods. In this study, the fault diagnosis method of analog circuits was studied. The fault feature vectors were extracted by a wavelet transform and then classified by a generalized regression neural network (GRNN). In order to improve the classification performance, a wolf pack algorithm (WPA) was used to optimize the GRNN, and a WPA-GRNN diagnosis algorithm was obtained. Then a simulation experiment was carried out taking a Sallen–Key bandpass filter as an example. It was found from the experimental results that the WPA could achieve the preset accuracy in the eighth iteration and had a good optimization effect. In the comparison between the GRNN, genetic algorithm (GA)-GRNN and WPA-GRNN, the WPA-GRNN had the highest diagnostic accuracy, and moreover it had high accuracy in diagnosing a single fault than multiple faults, short training time, smaller error, and an average accuracy rate of 91%. The experimental results prove the effectiveness of the WPA-GRNN in fault diagnosis of analog circuits, which can make some contributions to the further development of the fault diagnosis of analog circuits.

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Authors and Affiliations

Hui Wang
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Abstract

This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog- AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
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Bibliography

[1] N. Arora, “MOSFET Modeling for VLSl Circuit Simulation: Theory and Practice,” World Scientific, 1993.
[2] International Technology Roadmap for Semiconductors. Available: http://www.itrs2.net, 2017.
[3] O. Samy, H. Abdelhamid, Y. Ismail, A. Zekry, “A 2D compact model for lightly doped DGMOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs),” Microelectronics reliability, 2016, 67, 82-88.
[4] J-P. Colinge, “FinFETs and Other Multi-Gate Transistors,” Springer, 2008.
[5] A. Amara, “Planar Double-Gate Transistor, From Technology to Circuit,” Springer, 2009.
[6] D. Stefanović, M. Kayal, M, “Structured Analog CMOS Design,” Springer, 2008.
[7] A. Mangla, M.-A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectronics journal, 2013, 44, 570-575.
[8] A.B. Bhattacharyya, “Compact MOSFET models for VLSI design,” Wiley, 2009.
[9] B. Smaani, S. Latreche, B. Iñiguez, „Compact drain-current model for undoped cylindrical surrounding-gate MOSFETs including short channel effects,” J. Appl. Phys., 2013, 114.
[10] J-M. Sallese, F. Krummenacher, F. Prégaldiny, „A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism,” Solid-State Electronics, 2012, 49, 485-489.
[11] O. Moldovan, F. Lime, S. Barraud, B. Smaani, „Experimentally verified drain-current model for variable barrier transistor,” IET Electronics Letters, 2015, 51, 17, 364–366.
[12] J. Alvarado, B. Iñiguez, M. Estrada, “Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation,” Int. J. Numer. Model, 2010, 23, 88–106.
[13] O. Cobianu, M. Soffke, A. Glesner, “Verilog-A model of an undoped symmetric dual-gate MOSFET,” Int. Adv. Radio Sci, 2006, 4, 303–306.
[14] M. Cheralathan, E. Contreras, J. Alvarado, “Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models,” Microelectronics Journal, 2013, 44, 80–85. [15] Verilog-AMS User Manual, Accellera 2006.
[16] B. Smaani, M. Bella, S. Latreche, “Compact Modeling of Lightly Doped Nanoscale DG MOSFET Transistor,” Applied Mechanics and Materials, 2014, 492, 06–10.
[17] O. Samy, H. Abdelhamid , Y. Ismail, A. Zekry, “A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs),” Microelectronics Reliability, 2016, 67, 82-88.
[18] Y. Taur, X. Liang, “A continuous, analytic drain-current model for DG MOSFETs,” IEEE Electron device Letters, 2004, 25, 2, 107–109.
[19] J-M. Sallese, A. S. Porret, “A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation,” Solid-State Electronics, 2000, 44, 887-894.
[20] H. Børli, S. Kolberg, “Capacitance modeling of short-channel double-gate MOSFETs,” Solid-State Electronics, 2008, 52, 1486–1490.
[21] C. Enz, F. Krummenacher, A.Vittoz, “An analytical MOS Transistor Model Valid in All Regions of Operation Dedicated to low voltage and low current applications,” Analog and integrated Circuits and Signal Processing, 1995, 8, 83-114.
[22] M. Bella, S. Latreche, C. Gontrand, “Nanoscale DGMOSFET: DC modification and Analysis of Noise in RF Oscillator,” Journal of Applied Sciences,2015, 5, 800–807.
[23] R. Blaise, W. Tekam, J. Kengne, G. D. Kenmoe, “High frequency Colpitts’ oscillator: A simple configuration for chaos generation,” Chaos, Solitons & Fractals, 2019, 126, 351–360.
[24] A.Rana1, P. Gaikwad, “Colpitts oscillator: design and performance optimization,” Int. Journal of Applied Sciences and Engineering Research, 2014, 3, 913–919.
[25] SMASH User Manual Version 5.18 Release, 2012.
[26] Device simulator ATLAS, Silvaco International, 2007.
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Authors and Affiliations

Billel Smaani
1
Yacin Meraihi
2
Fares Nafa
2
Mohamed Salah Benlatreche
3
Hamza Akroum
4
Saida Latreche
5

  1. Ingénierie des Systémes Electriques Department, Faculty of Technology, Boumerdes University, Algeria
  2. Laboratoire d'Ingénierie et Systèmes de Télécommunications, Faculté de Technologie, Boumerdes, Algeria
  3. Centre Universitaire Abdel Hafid Boussouf Mila, Algeria
  4. Laboratoire d’Automatique Appliquée, Université M’Hamed Bougara de Boumerdes, Algeria
  5. Laboratoire Hyperfréquences et Semiconducteurs, Electronique Department, Constantine 1 University, Algeria
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Abstract

Correct incipient identification of an analog circuit fault is conducive to the health of the analog circuit, yet very difficult. In this paper, a novel approach to analog circuit incipient fault identification is presented. Time responses are acquired by sampling outputs of the circuits under test, and then the responses are decomposed by the wavelet transform in order to generate energy features. Afterwards, lower-dimensional features are produced through the kernel entropy component analysis as samples for training and testing a one-against-one least squares support vector machine. Simulations of the incipient fault diagnosis for a Sallen-Key band-pass filter and a two-stage four-op-amp bi-quad low-pass filter demonstrate the diagnosing procedure of the proposed approach, and also reveal that the proposed approach has higher diagnosis accuracy than the referenced methods.
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Authors and Affiliations

Chaolong Zhang
Yigang He
Lei Zuo
Jinping Wang
Wei He
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Abstract

In order to make the analog fault classification more accurate, we present a method based on the Support Vector Machines Classifier (SVC) with wavelet packet decomposition (WPD) as a preprocessor. In this paper, the conventional one-against-rest SVC is resorted to perform a multi-class classification task because this classifier is simple in terms of training and testing. However, this SVC needs all decision functions to classify the query sample. In our study, this classifier is improved to make the fault classification task more fast and efficient. Also, in order to reduce the size of the feature samples, the wavelet packet analysis is employed. In our investigations, the wavelet analysis can be used as a tool of feature extractor or noise filter and this preprocessor can improve the fault classification resolution of the analog circuits. Moreover, our investigation illustrates that the SVC can be applicable to the domain of analog fault classification and this novel classifier can be viewed as an alternative for the back-propagation (BP) neural network classifier.

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Authors and Affiliations

Jiang Cui
Youren Wang
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Abstract

A simple analog circuit is presented which can play a neuron role in static-model-based neural networks implemented in the form of an integrated circuit. Operating in a transresistance mode it is suited to cooperate with transconductance synapses. As a result, its input signal is a current which is a sum of currents coming from the synapses. Summation of the currents is realized in a node at the neuron input. The circuit has two outputs and provides a step function signal at one output and a linear function one at the other. Activation threshold of the step output can be conveniently controlled by means of a voltage. Having two outputs, the neuron is attractive to be used in networks taking advantage of fuzzy logic. It is built of only five MOS transistors, can operate with very low supply voltages, consumes a very low power when processing the input signals, and no power in the absence of input signals. Simulation as well as experimental results are shown to be in a good agreement with theoretical predictions. The presented results concern a 0.35 1m CMOS process and a prototype fabricated in the framework of Europractice.

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Authors and Affiliations

R. Wojtyna
T. Talaśka

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