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Number of results: 8
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Abstract

A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.
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Authors and Affiliations

Jelena Lukić
Dragan Denić
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Abstract

The Histogram Test method is a popular technique in analog-to-digital converter (ADC) testing. The presence of additive noise in the test setup or in the ADC itself can potentially affect the accuracy of the test results. In this study, we demonstrate that additive noise causes a bias in the terminal based estimation of the gain but not in the estimation of the offset. The estimation error is determined analytically as a function of the sinusoidal stimulus signal amplitude and the noise standard deviation. We derive an exact but computationally difficult expression as well as a simpler closed form approximation that provides an upper bound of the bias of the terminal based gain. The estimators are validated numerically using a Monte Carlo procedure with simulated and experimental data.

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Authors and Affiliations

F. Alegria
Nestor Tiglao
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Abstract

Time-interleaved analog-to-digital converter (ADC) architecture is crucial to increase the maximum sample rate. However, offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the performance of time-interleaved ADCs. This paper focuses on the gain mismatch and timing error. Techniques based on Discrete Fourier Transform (DFT) for estimating and correcting gain mismatch and timing error in an M-channel ADC are depicted. Numerical simulations are used to verify the proposed estimation and correction algorithm.

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Authors and Affiliations

Lianping Guo
Shulin Tian
Zhigang Wang
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Abstract

This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. Development of mathematical models of errors, quantitative assessment of these errors taking into account modern components and assessing the accuracy of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback were presented. (Logarithmic ADC with accumulation of charge and impulse feedback – analysis and modeling).
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Bibliography

[1] S. Purighalla, B. Maundy, “84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18-μm Technology,” IEEE Transactions on Circuits and Systems II: Express Briefs, 58 (2011), no.5, pp. 279-283
[2] J. Lee, J. Kang, S. Park, J. Seo, J. Anders, J. Guilherme, M. P. Flynn, “A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC,” IEEE Journal Of Solid-State Circuits, 44 (2009), no.10, pp. 2755-2765
[3] B. Maundy, D. Westwick, S. Gift, “On a class of pseudo-logarithmic amplifiers suitable for use with digitally switched resistors,” Int. J. of Circuit Theory and Applications, vol. 36 (2008), no.1, pp. 81–108
[4] B. Maundy, D. Westwick, S. Gift, (2007) “A useful pseudo-logarithmic circuit,” Microelectronics International, Vol. 24 Iss: 2, pp.35 - 45
[5] M. Alirieza, L. Jing and J. Dileepan, “Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture,” Sensors, 13(8), pp. 10765-10782, August 2013
[6] J. Guilherme, J. Vital, Jose Franca, “A True Logarithmic Analog-to-Digital Pipeline Convener with 1.5bitistage and Digital Correction,” Proc. IEEE International Conference on Electronics Circuits and Systems, pp. 393-396, Malta 2001
[7] G. Bucci, M. Faccio, C. Landi, “The performance test of a piece-linear A/D converter,” IEEE Instrumentation and Measurement Technology Conference, St. Paul USA May 1998, pp.1223.1228
[8] J. Guilherme, J. Vital, J. Franca, “A CMOS Logarithmic Pipeline A/D Converter with a Dynamic Range of 80 dB,” IEEE Electronics, Circuits and Systems, 2002. 9th International Conference on, (2002), no.3/02, pp. 193-196
[9] J. Sit and R. Sarpeshkar, “A Micropower Logarithmic A/D With Offset and Temperature Compensation,” IEEE J. Solid-State Circuits, 39 (2004), nr. 2, pp. 308-319
[10] J. Mahattanakul, “Logarithmic data converter suitable for hearing aid applications,” Electronic Letters, 41 (2005), no.7, pp. 31-32
[11] S. Sirimasakul, A. Thanachayanont, W. Jeamsaksiri, “Low-Power Current-Mode Logarithmic Pipeline Analog-to-Digital Converter for ISFET based pH Sensor,” IEEE ISCIT, 2009, no.6/09, pp. 1340-1343
[12] M. Santosa, N. Hortaa, J. Guilherme, “A survey on nonlinear analog-to-digital converters,” Integration, the VLSI Journal, Volume 47, Issue 1, pp. 12–22, January 2014
[13] Z.R. Mychuda, “Logarithmic Analog-To-Digital Converters – ADC of the Future,” Prostir, Lviv, Ukraine 2002, pp. 242
[14] A. Szcześniak, Z Myczuda, “A method of charge accumulation in the logarithmic analog-to-digital converter with a successive approximation,” Electrical Review, 86 (2010), no.10, pp. 336-340
[15] A. Szcześniak, U. Antoniw, Ł. Myczuda, Z. Myczuda, „Logarytmiczne przetworniki analogowo-cyfrowe z nagromadzeniem ładunku i impulsowym sprzężeniem zwrotnym,” Electrical Review, R. 89 no. 8/2013, pp. 277 – 281
[16] A. Szcześniak, Z. Myczuda, „Analiza prądów upływu logarytmicznego przetwornika analogowo-cyfrowego z sukcesywną aproksymacją,” Electrical Review, 88 (2012), no. 5а, pp. 247-250
[17] J.H. Moon, D. Y. Kim, M. K. Song, Patent No. KR20110064514A, “Logarithmic Single-Slope Analog Digital Convertor, Image Sensor Device And Thermometer Using The Same, And Method For Logarithmic Single-Slope Analog Digital Converting,”
[18] J. Gorisse, F. A. Cathelin, A. Kaiser, E. Kerherve Patent No. EP2360838A1, “Method for logarithmic analog-to-digital conversion of an analog input signal and corresponding apparatus,”
[19] R. Offen Patent No. DE102008007207A1 “Logarithmierender Analog-Digital Wandler,”
[20] H. Suzunaga Patent No. US20080054163A1, “Logarithmic-compression analog-digital conversion circuit and semiconductor photosensor device,”
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Authors and Affiliations

Zynoviy Mychuda
1
Lesya Mychuda
1
Uliana Antoniv
1
Adam Szcześniak
2

  1. Lviv Polytechnic National University, Department of the Computer-Assisted Systems of Automation, Ukraine
  2. University of Technology in Kielce, Department of Mechatronics and Machine Building, Poland
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Abstract

This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. LADC construction, principle of operation and dynamic properties were presented. They can also be part of more complex converters and systems based on LADC. LADC of this class is perspective for implementation in the form of integrated circuit, as the number of switched capacitors needed to conversion is minimized to one capacitor. (Logarithmic ADC with accumulation of charge and impulse feedback – construction, principle of operation and dynamic properties)
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Bibliography

[1] S. Purighalla, B. Maundy, “84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18-μm Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, 58 (2011), no.5, pp. 279-283
[2] J. Lee, J. Kang, S. Park, J. Seo, J. Anders, J. Guilherme, M. P. Flynn, “A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC,” IEEE Journal Of Solid-State Circuits, 44 (2009), no.10, pp. 2755-2765
[3] B. Maundy, D. Westwick, S. Gift, “On a class of pseudo-logarithmic amplifiers suitable for use with digitally switched resistors,” Int. J. of Circuit Theory and Applications, vol. 36 (2008), no.1, pp. 81–108
[4] B. Maundy, D. Westwick, S. Gift, (2007) “A useful pseudo-logarithmic circuit,” Microelectronics International, Vol. 24 Iss: 2, pp.35 - 45
[5] M. Alirieza, L. Jing and J. Dileepan, “Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture,” Sensors, 13(8), pp. 10765- 10782, August 2013
[6] J. Guilherme, J. Vital, Jose Franca, “A True Logarithmic Analog-to- Digital Pipeline Convener with 1.5bitistage and Digital Correction,” Proc. IEEE International Conference on Electronics Circuits and Systems, pp. 393-396, Malta 2001
[7] G. Bucci, M. Faccio, C. Landi, “The performance test of a piece-linear A/D converter,” IEEE Instrumentation and Measurement Technology Conference, St. Paul USA May 1998, pp.1223.1228
[8] J. Guilherme, J. Vital, J. Franca, “A CMOS Logarithmic Pipeline A/D Converter with a Dynamic Range of 80 dB,” IEEE Electronics, Circuits and Systems, 2002. 9th International Conference on, (2002), no.3/02, pp. 193-196
[9] J. Sit and R. Sarpeshkar, “A Micropower Logarithmic A/D With Offset and Temperature Compensation,” IEEE J. Solid-State Circuits, 39 (2004), nr. 2, pp. 308-319
[10] J. Mahattanakul, “Logarithmic data converter suitable for hearing aid applications,” Electronic Letters, 41 (2005), no.7, pp. 31-32
[11] S. Sirimasakul, A. Thanachayanont, W. Jeamsaksiri, “Low-Power Current-Mode Logarithmic Pipeline Analog-to-Digital Converter for ISFET based pH Sensor,” IEEE ISCIT, 2009, no.6/09, pp. 1340-1343
[12] M. Santosa, N. Hortaa, J. Guilherme, “A survey on nonlinear analog-todigital converters,” Integration, the VLSI Journal, Volume 47, Issue 1, pp. 12–22, January 2014
[13] Z.R. Mychuda, “Logarithmic Analog-To-Digital Converters – ADC of the Future,” Prostir, Lviv, Ukraine 2002, pp. 242
[14] A. Szcześniak, Z Myczuda, “A method of charge accumulation in the logarithmic analog-to-digital converter with a successive approximation,” Electrical Review, 86 (2010), no.10, pp. 336-340
[15] A. Szcześniak, U. Antoniw, Ł. Myczuda, Z. Myczuda, „Logarytmiczne przetworniki analogowo-cyfrowe z nagromadzeniem ładunku i impulsowym sprzężeniem zwrotnym,” Electrical Review, R. 89 no. 8/2013, pp. 277 – 281
[16] A. Szcześniak, Z. Myczuda, „Analiza prądów upływu logarytmicznego przetwornika analogowo-cyfrowego z sukcesywną aproksymacją,” Electrical Review, 88 (2012), no. 5а, pp. 247-250
[17] J.H. Moon, D. Y. Kim, M. K. Song, Patent No. KR20110064514A, “Logarithmic Single-Slope Analog Digital Convertor, Image Sensor Device And Thermometer Using The Same, And Method For Logarithmic Single-Slope Analog Digital Converting,”
[18] J. Gorisse, F. A. Cathelin, A. Kaiser, E. Kerherve Patent No. EP2360838A1, “Method for logarithmic analog-to-digital conversion of an analog input signal and corresponding apparatus,”
[19] R. Offen Patent No. DE102008007207A1 “Logarithmierender Analog- Digital Wandler,”
[20] H. Suzunaga Patent No. US20080054163A1, “Logarithmic-compression analog-digital conversion circuit and semiconductor photosensor device,”
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Authors and Affiliations

Zynoviy Mychuda
1
Lesya Mychuda
1
Uliana Antoniv
1
Adam Szcześniak
2

  1. Lviv Polytechnic National University, Department of the Computer-Assisted Systems of Automation, Ukraine
  2. University of Technology in Kielce, Department of Mechatronics and Machine Building, Poland
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Abstract

The authors update the issue disassembly-free control and correction of all components of the error of measuring channels with multi-bit analog-to-digital converters (ADCs). The main disadvantages of existing methods for automatic control of the parameters of multi-bit ADCs, in particular their nonlinearity, are identified. Methods for minimizing instrumental errors and errors caused by limited internal resistances of closed switches, input and output resistances of active elements are investigated. The structures of devices for determining the multiplicative and nonlinear components of the error of multi-bit ADCs based on resistive dividers built on single-nominal resistors are proposed and analyzed. The authors propose a method for the correction of additive, multiplicative and nonlinear components of the error at each of the specified points of the conversion range during non-disassembly control of the ADC with both types of inputs. The possibility of non-disassembly control, as well as correction of multiplicative and nonlinear components of the error of multi-bit ADCs in the entire range of conversion during their on-site control is proven. ADC error correction procedures are proposed. These procedures are practically invariant to the non-informative parameters of active structures with resistive dividers composed of single-nominal resistors. In the article the prospects of practical implementation of the method of error correction during non-dismantling control of ADC parameters using the possibilities provided by modern microelectronic components are shown. The ways to minimize errors are proposed and the requirements to the choice of element parameters for the implementation of the proposed technical solutions are given. It is proved that the proposed structure can be used for non-disassembly control of multiplicative and nonlinear components of the error of precision instrumentation amplifiers.
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Authors and Affiliations

Tetiana Bubela
1
Roman Kochan
2 3
Łukasz Więcław
2
Vasyl Yatsuk
1
Viktor Kuts
1
Jurij Yatsuk
4

  1. Lviv Polytecnic National University, Department of Information and Measurement Technologies, S. Bandery 12, 79013 Lviv, Ukraine
  2. University of Bielsko-Biala, Department of Informatics and Automation, Willowa 2, 43-309 Bielsko-Biała, Poland
  3. Lviv Polytecnic National University, Department of Specialized Computer Systems, S. Bandery 12, 79013 Lviv, Ukraine
  4. Lviv Polytecnic National University, Department of Computerized Automation Systems, S. Bandery 12, 79013 Lviv, Ukraine
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Abstract

This paper provides an overview of the effects of timing jitter in audio sampling analog-to-digital converters (ADCs), i.e. PCM (conventional or Nyquist sampling) ADCs and sigma-delta (ΣΔ) ADCs. Jitter in a digital audio is often defined as short-term fluctuations of the sampling instants of a digital signal from their ideal positions in time. The influence of the jitter increases particularly with the improvements in both resolution and sampling rate of today's audio ADCs. At higher frequencies of the input signals the sampling jitter becomes a dominant factor in limiting the ADCs performance in terms of signal-to-noise ratio (SNR) and dynamic range (DR).

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Authors and Affiliations

Zbigniew Kulka
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Abstract

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 megasamples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
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Bibliography

[1] Y. Zhou, B. Xu and Y. Chiu, “A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC,” IEEE Journal of Solid-State Circuits 54, 8, 2207-2218, (2019). https://doi.org/10.1109/JSSC.2019.2915583.
[2] D. Oh, J. Kim, D. Jo, W. Kim, D. Chang and S. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” IEEE Journal of Solid-State Circuits 54, 1, 288- 297,(2019). https://doi.org/10.1109/JSSC.2018.2870554.
[3] A. Wu, J. Wu, and J. Huang, “Energy-efficient switching scheme for ultra-low voltage SAR ADC.”, Analog Integr Circ Sig Process 90, 507–511, (2017). https://doi.org/10.1007/s10470-016-0892-0
[4] M. Guo, J. Mao, S. Sin, H. Wei and R. P. Martins, “A 1.6- GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration,”IEEE Journal of Solid-State Circuits 55, 3,693-705, (2020). https://doi.org/10.1109/JSSC.2019.2945298.
[5] M. Davidovic, G. Zach, H. Zimmermann, “An 11-bit successive approximation analog-to-digital converter based on a combined capacitor-resistor network.”, Elektrotech. Inftech. 127, 98–102, (2010). https://doi.org/10.1007/s00502-010-0704-7
[6] D. Chang, W. Kim, M. Seo, H. Hong, and S. Ryu, “Normalized- Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.”, IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, 322-332 (2017). https://doi.org/10.1109/TCSI.2016.2612692
[7] M. Shim et al.,“Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC”, IEEE Journal of Solid-State Circuits 52, 4, 1077-1090, (2017). https://doi.org/10.1109/JSSC.2016.2631299
[8] D. Zhang and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs 63, 3, 244-248, (2016). https://doi.org/10.1109/TCSII.2015.2482618.
[9] S.A. Zahrai, M. Onabajo, “ Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power- Efficient Hybrid Data Converters.”, J. Low Power Electron. Appl. 8, 12, (2018). https://doi.org/10.3390/jlpea8020012
[10] S.Taheri, J. Lin, J. S. Yuan,“Security Interrogation and Defense for SAR Analog to Digital Converter.”, Electronics 6, 48, (2017). https://doi.org/10.3390/electronics6020048
[11] J. Kim, B. Sung, W. Kim and S. Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS”, IEEE Journal of Solid-State Circuits 48, 6, 1429-1441, (2013). https://doi.org/10.1109/JSSC.2013.2252516
[12] S. Danesh, J. Hurwitz, K. Findlater, D. Renshaw and R. Henderson, “A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design”, IEEE Journal of Solid-State Circuits 48, 3, 733-748, (2013). https://doi.org/10.1109/JSSC.2013.2237672
[13] L. Wang, M. LaCroix and A. C. Carusone, “A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.”, IEEE Transactions on Circuits and Systems II: Express Briefs 64, 12, 1367-1371, (2017). https://doi.org/10.1109/TCSII.2017.2726063
[14] F. M´arquez, et al., “A novel autozeroing technique for flash Analog-to-Digital converters.”, Integration 47, 1, 23-29, (2014). https://doi.org/10.1016/j.vlsi.2013.06.002
[15] Masumeh Damghanian, Seyed Javad Azhari, “A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications.”, Integration 57, 158-168, (2017). https://doi.org/10.1016/j.vlsi.2017.01.006
[16] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan and J. J. Liou, “A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage,” IEEE Access 7, 93396- 93403,(2019). https://doi.org/10.1109/ACCESS.2019.2927514.
[17] A. Khatak, M. Kumar, S. Dhull, “An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits.”, J. Low Power Electron. Appl. 8, 33, (2018). https://doi.org/10.3390/jlpea8040033.
[18] B. Hershberg et al., “3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA 68-70, (2019). https://doi.org/10.1109/ISSCC.2019.8662319.
[19] U. Chio et al., “Design and Experimental Verification of a Power Effective Flash-SAR Sub ranging ADC.”, IEEE Transactions on Circuits and Systems II: Express Briefs 57, 8, 607-611, (2010). https://doi.org/10.1109/TCSII.2010.2050937
[20] Young-Deuk Jeon et al., “A dual-channel pipelined ADC with sub-ADC based on flash-SAR architecture.”, Circuits and Systems II: Express Briefs 59, 741-745. (2012). https://doi.org/10.1109/TCSII.2012.2222837
[21] Y. Lin et al.,“ A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.”, IEEE Transactions on Circuits and Systems I: Regular Papers 60, 3, 570-581, (2013). https://doi.org/10.1109/TCSI.2012.2215756
[22] J.I. Lee, J. Song, “Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count.”, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) 1-4, (2013). https://doi.org/10.1109/TENCON.2013.6718487
[23] A. Esmailiyan, F. Schembari and R. B. Staszewski, “A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump- Based Comparators in 28-nm CMOS,”IEEE Transactions on Circuits and Systems I: Regular Papers 67, 6, 1789-1802, (2020). https://doi.org/10.1109/TCSI.2020.2969804.
[24] J. Xu, et al., “Low-leakage analog switches for low-speed sample-and-hold circuits”, Microelectronics Journal 76, 22–27, (2018). https://doi.org/10.1016/j.mejo.2018.04.008
[25] M. Nazari, L. Sharifi,A. Aghajani, and O. Hashemipour, “A 12-bit high performance current-steering DAC using a new binary to thermometer decoder.”, 2016 24 Iranian Conference on Electrical Engineering (ICEE), Shiraz 2016 1919-1924, (2016). https://doi.org/10.1109/IranianCEE.2016.7585835
[26] H.S. Bindra et al., “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.”, IEEE Journal of Solid-State Circuits 53, 7, 1902-1912, (2018). https://doi.org/10.1109/JSSC.2018.2820147
[27] A. Taghizadeh, Z.D. Koozehkanani, J. Sobhi, “A new high-speed lowpower and low-offset dynamic comparator with a current-mode offset compensation technique.”, AEU - Int. J. Electron. Commun. 81, 163–170, (2018). https://doi.org/10.1016/j.aeue.2017.07.018.
[28] M. Saberi and R. Lotfi,“ Segmented Architecture for Successive Approximation Analog-to-Digital Converters.”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 3, 593-606, (2014). https://doi.org/10.1109/TVLSI.2013.2246592
[29] Y. Haga et al., “Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique.”, 2005 IEEE International Symposium on Circuits and Systems 1, 220-223, (2005). https://doi.org/10.1109/ISCAS.2005.1464564.
[30] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone- Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits 54, 3, 646-658, (2019). https://doi.org/10.1109/JSSC.2018.2889680.
[31] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC,” IEEE Journal of Solid-State Circuits 50, 12, 2901-2911, (2015). https://doi.org/10.1109/JSSC.2015.2463094
[32] B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.”, IEEE Communications Magazine 54, 4, 78-83, (2016). https://doi.org/10.1109/MCOM.2016.7452270
[33] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur196-199, (2010). https://doi.org/10.1109/APCCAS.2010.5774747.
[34] M. Hotta et al., “SAR ADC Architecture with Digital Error Correction.”. IEEJ Trans Elec Electron Eng 5, 651-659, (2010). https://doi.org/10.1002/tee.20588
[35] S. Lee, A.P. Chandrakasan and H. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC with Background Timing Skew Calibration.”, IEEE Journal of Solid-State Circuits 49, 12, 2846-2856, (2014). https://doi.org/10.1109/JSSC.2014.2362851
[36] M. Damghanian and S.J. Azhari, “A novel three-section encoder in a low-power 2.3 GS/s flash ADC.”, Microelectronics J 82, 71–80, (2018). https://doi.org/10.1016/j.mejo.2018.10.009
[37] Yi. Shen and Z. Zhu, “Analysis and optimization of the twostage pipelined SAR ADCs.”, Microelectronics Journal 47, 1–5, (2016). https://doi.org/10.1016/j.mejo.2015.10.018.
[38] Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu,“A 10-bit 100-MS/s 5.23 mW SAR ADC in 0.18 μm CMOS.”,Microelectronics Journal 78, 63-72, (2018). https://doi.org/10.1016/j.mejo.2018.06.007
[39] X. Xin et al.,“A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip.”,Microelectronics Journal 83, 104–116, (2019). https://doi.org/10.1016/j.mejo.2018.11.017
[40] W. Guo, S. Liu, and Z. Zhu, “ An asynchronous 12-bit 50MS/s rail-torail Pipeline-SAR ADC in 0.18 μm CMOS.”, Microelectronics Journal 52, 23–30, (2016). https://doi.org/10.1016/j.mejo.2016.03.003
[41] B. Samadpoor Rikan et al.,“A 10-bit 1 MS / s segmented Dual-Sampling SAR ADC with reduced switching energy.”, Microelectronics Journal 70, 89–96, (2017). https://doi.org/10.1016/j.mejo.2017.11.005
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Authors and Affiliations

Anil Khatak
1
ORCID: ORCID
Manoj Kumar
2
Sanjeev Dhull
3

  1. Faculty of Biomedical Engineering, GJUS&T, Hisar, Haryana, India
  2. Faculty of USICT, Guru Gobind Singh Indraprastha University, New Delhi, India
  3. Faculty of ECE, GJUS&T, Hisar, Haryana, India

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