Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 20
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

The separation of variables approach to formulate the averaged models of DC-DC switch-mode power converters is presented in the paper. The proposed method is applied to basic converters such as BUCK, BOOST and BUCK-BOOST. The ideal converters or converters with parasitic resistances, working in CCM and in DCM mode are considered. The models are presented in the form of equation systems for large signal, steady-state and small-signal case. It is shown, that the models obtained by separation of variables approach differ in some situations from standard models based on switch averaging method.

Go to article

Authors and Affiliations

Włodzimierz Janke
Download PDF Download RIS Download Bibtex

Abstract

The averaged models of switch-mode DC-DC power converters are discussed. Two methods of averaged model derivation are considered - the first, based on statespace averaging and the second, on the switch averaging approach. The simplest converters: BUCK, BOOST and BUCK-BOOST working in CCM (continuous conduction mode) or DCM are taken as examples in detailed considerations. Apart from the ideal converters, the more realistic case of converters with parasitic resistances is analyzed. The switch averaging approach is used more frequently than the other and is believed to be more convenient in practical applications. It is shown however, that in the deriving the averaged models based on the switch-averaging approach, some informalities have been made, which may be the source of errors in the case of converters with parasitic resistances, or working in DCM mode.

Go to article

Authors and Affiliations

Włodzimierz Janke
Download PDF Download RIS Download Bibtex

Abstract

In the constant pursue of the sustainability of socio-industrial systems, the definition of useful, reliable and informative, and at the same time simple and transparent, indicators is an important step for the evaluation of the circularity of the assessed systems. In the circular economy (CE) context, scientific literature has already identified the lack of overarching indicators (social, urban, prevention-oriented, etc.), pointing out that mono-dimensional indicators are not able to grasp the complexity of the systemic, closed-loop, feedback features of CE. In this respect, Emergy accounting is one of the approaches that have been identified as holding the potential to capture both resource generation and product delivery dimensions and therefore to provide an enhanced systems’ evaluation in a CE perspective.

Because of Emergy’s intrinsic definition and its calculation structure, Emergy-based indicators conceptually lend themselves very well to the evaluation and monitoring of circular processes. Additionally, Emergy has the unique feature of enabling the evaluation of systems that are not necessarily only technosphere systems, but also of technological systems which embed nature (techno-ecological systems).

The present paper gives a perspective on a set of Emergy-based indicators that we have identified as suitable to evaluate circular systems, and outlines the different perspective compared to the circularity indicators defined in the “Circularity Indicators Project” launched by the Ellen MacArthur Foundation.

Go to article

Authors and Affiliations

Antonino Marvuglia
Remo Santagata
Benedetto Rugani
Enrico Benetto
Sergio Ulgiati
Download PDF Download RIS Download Bibtex

Abstract

The paper presents new ensemble solutions, which can forecast the average level of particulate matters PM10 and PM2.5 with increased accuracy. The proposed network is composed of weak predictors integrated into a final expert system. The members of the ensemble are built based on deep multilayer perceptron and decision tree and use bagging and boosting principle in elaborating common decisions. The numerical experiments have been carried out for prediction of daily average pollution of PM10 and PM2.5 for the next day. The results of experiments have shown, that bagging and boosting ensembles employing these weak predictors improve greatly the quality of results. The mean absolute errors have been reduced by more than 30% in the case of PM10 and 20% in the case of PM2.5 in comparison to individually acting predictors.

Go to article

Authors and Affiliations

D. Triana
S. Osowski
Download PDF Download RIS Download Bibtex

Abstract

In this paper, the power factor correction system consisted of: bridge converter, parallel resonant circuit, high frequency transformer, diode rectifier and LFCF filter is presented. This system is controlled by a pulse density modulation method and the principle of its operation is based on the boost technique. The modeling approach is illustrated by an example using AC/HF/DC converter. Verification of the derived model is provided, which demonstrated the validity of the proposed approach.
Go to article

Authors and Affiliations

Antoni Bogdan
Download PDF Download RIS Download Bibtex

Abstract

This elaboration presents the concept of a unidirectional DC–DC switchedcapacitor converter operating as a voltage tripler. The system consists of two resonant cells with switched capacitors and chokes. This proposed converter topology achieves low voltages on semiconductor switches (diodes and transistors) compared to the classic SC series-parallel converter or the boost topology. The output voltage on the capacitors is reduced in the proposed converter because it is divided into two series-connected capacitors with asymmetric distribution. The presented results describe the analytical description of the system operation and the analytical equation for semiconductor currents. A simulation and experimental results have been performed. The system efficiency and three voltage gain values were measured in the experimental setup. The efficiency measured was also compared with the analytical determination curve for loss analysis and further converter optimization.
Go to article

Authors and Affiliations

Maciej Chojowski
1
Robert Sosnowski
1
Marcin Baszyński
1

  1. AGH University of Science and Technology, Poland
Download PDF Download RIS Download Bibtex

Abstract

The purpose of this paper is to propose a model of a novel quasi-resonant boost converter with a tapped inductor. This converter combines the advantages of zero voltage quasi-resonant techniques and different conduction modes with the possibility of obtaining a high voltage conversion ratio by using a tapped inductor, which results in high converter efficiency and soft switching in the whole output power range. The paper contains an analysis of converter operation, a determination of voltage conversion ratio and the maximum voltage across power semiconductor switches as well as a discussion of control methods in discontinuous, critical, and continuous conduction modes. In order to verify the novelty of the proposed converter, a laboratory prototype of 300 W power was built. The highest efficiency η  = 94.7% was measured with the output power Po =  260 W and the input voltage Vin = 50 V. The lowest efficiency of 90.7% was obtained for the input voltage Vin  = 30 V and the output power Po = 75 W. The model was tested at input voltages (30–50) V, output voltage 380 V and maximum switching frequency 100 kHz.

Go to article

Bibliography

  1.  M. Forouzesh, Y.P. Siwakoti, S.A. Gorji, F. Blaabjerg, and B. Lehman, “Step-Up DC-DC Converters: A Comprehensive Review of Voltage-Boosting Techniques, Topologies, and Applications”, IEEE Trans. Power Electron. 32(12), 9143‒9178 (2017), doi: 10.1109/ TPEL.2017.2652318.
  2.  W. Li and X. He, “Review of Nonisolated High-Step-Up DC/DC Converters in Photovoltaic Grid-Connected Applications”, IEEE Trans. Ind. Electron. 58(4), 1239‒1250 (2011), doi: 10.1109/TIE.2010.2049715.
  3.  H. Liu, H. Hu, H. Wu, Y. Xing, and I. Batarseh, “Overview of High-Step-Up Coupled-Inductor Boost Converters”, IEEE IEEE J. Emerg. Sel. Top. Power Electron. 4(2), 689‒704 (2016), doi: 10.1109/JESTPE.2016.2532930.
  4.  A. Tomaszuk and A. Krupa, “High efficiency high step-up DC/DC converters – a review”, Bull. Pol. Ac.: Tech. 59(4), 475‒483 (2011), doi: 10.2478/v10175-011-0059-1.
  5.  W. Janke, M. Bączek, and J. Kraśniewski, “Input characteristics of a non-ideal DC-DC flyback converter”, Bull. Pol. Ac.: Tech. 67(5), 841‒849 (2019), doi: 10.24425/bpasts.2019.130884.
  6.  F.C. Lee, “High-frequency quasi-resonant converter technologies”, Proc. IEEE 76(4), 377‒390 (1988), doi: 10.1109/5.4424.
  7.  W.A. Tabisz, P.M. Gradzki, and F.C.Y. Lee, “Zero-voltage-switched quasi-resonant buck and flyback converters-experimental results at 10 MHz”, IEEE Trans. Power Electron. 4(2), 194‒204, 1989, doi: 10.1109/63.24904.
  8.  M. Harasimczuk and A. Borchert, “Single switch quasi-resonant ZVS converter with tapped inductor”, Prz. Elektrotechniczny 3, 44‒48 (2018).
  9.  S. Sathyan, H.M. Suryawanshi, M.S. Ballal, and A.B. Shitole, “Soft-Switching DC-DC Converter for Distributed Energy Sources With High Step-Up Voltage Capability”, IEEE Trans. Ind. Electron. 62(11), 7039‒7050 (2015), doi: 10.1109/TIE.2015.2448515.
  10.  T.F. Wu, Y.S. Lai, J.C. Hung, and Y.M. Chen, “Boost Converter With Coupled Inductors and Buck-Boost Type of Active Clamp”, IEEE Trans. Ind. Electron. 55(1), 154‒162 (2008), doi: 10.1109/TIE.2007.903925.
  11.  J.H. Yi, W. Choi, and B.H. Cho, “Zero-Voltage-Transition Interleaved Boost Converter With an Auxiliary Coupled Inductor”, IEEE Trans. Power Electron. 32(8), 5917‒5930 (2017), doi: 10.1109/TPEL.2016.2614843.
  12.  Y. Chen, Z. Li, and R. Liang, “A Novel Soft-Switching Interleaved Coupled-Inductor Boost Converter With Only Single Auxiliary Circuit”, IEEE Trans. Power Electron. 33(3), 2267‒2281 (2018), doi: 10.1109/TPEL.2017.2692998.
  13.  R. Stala et al., “A family of high-power multilevel switched capacitor-based resonant DC-DC converters – operational parameters and novel concepts of topologies”, Bull. Pol. Ac.: Tech. 65(5), 639‒651 (2017).
  14.  M. Harasimczuk, “A QR-ZCS Boost Converter With Tapped Inductor and Active Edge-Resonant Cell”, IEEE Trans. Power Electron. 35(12), 13085‒13095 (2020), doi: 10.1109/TPEL.2020.2991363.
  15.  M. Harasimczuk, “Przekształtniki podwyższające napięcie z dławikami dzielonymi”, PL Patent, Poland, P.423354, 2017.
Go to article

Authors and Affiliations

Jakub Dawidziuk
1
ORCID: ORCID
Michał Harasimczuk
2
ORCID: ORCID

  1. Department of Automatic Control and Robotics, Bialystok University of Technology, ul. Wiejska 45D, 15-351 Bialystok, Poland
  2. Department of Electrical Engineering, Power Electronics and Electrical Power Engineering, Bialystok University of Technology, ul. Wiejska 45D, 15-351 Bialystok, Poland
Download PDF Download RIS Download Bibtex

Abstract

Large-signal input characteristics of three DC–DC converter types: buck, boost and flyback working in the discontinuous conduction mode (DCM), obtained by precise large signal PSpice simulations, calculations based on averaged models and measurements are presented. The parasitic resistances of the converter components are included in the simulations. The specific features of the input characteristics in theDCMand the differences between the continuous conduction mode (CCM) and DCM are discussed.

Go to article

Authors and Affiliations

Włodzimierz Janke
ORCID: ORCID
Maciej Bączek
ORCID: ORCID
Jarosław Kraśniewski
ORCID: ORCID
Marcin Walczak
Download PDF Download RIS Download Bibtex

Abstract

Large-signal input characteristics of three DC–DC converter types: buck, boost and flyback working in the continuous conduction mode (CCM), obtained by simulations and measurements are investigated. The results of investigations are presented in the form of the analytical formulas and the exemplary results of the measurements and two forms of simulations: based on the full description of the converter components and on the averaged models. The parasitic resistances of the converter components are included in the simulations and their influence on the simulation results is discussed.

Go to article

Authors and Affiliations

Włodzimierz Janke
ORCID: ORCID
Maciej Bączek
ORCID: ORCID
Jarosław Kraśniewski
ORCID: ORCID
Marcin Walczak
Download PDF Download RIS Download Bibtex

Abstract

The paper treats about main problems of one phase DC-AC microinverters that allow single solar cell to be joined with the grid. One of the issues is to achieve high voltage gain with high efficiency in DC circuit, which is necessary for proper operation of inverter. The operating principles, results of practical implementation and investigations on boost-flyback converter, which meets mentioned demands, are presented. (high step-up DC-DC boost-flyback converter for single phase grid microinverter).
Go to article

Authors and Affiliations

Adam Kawa
Stanisław Piróg
Adam Penczek
Download PDF Download RIS Download Bibtex

Abstract

This paper presents a concept and the results of an investigation of a DC–DC boost converter with high voltage gain and a reduced number of switches. The novel concept assumes that the converter operates in a topology composed of series connection switched- capacitor-based multiplier (SCVM) sections. Furthermore, the structure of the sections has significant impact on parameters of the converter which is discussed in this paper. The paper demonstrates the basic benefit such a multisection SCVM idea in the converter, which is the significant reduction in the number of switches and diodes for high voltage gain in comparison to an SCVM converter. Aside from the number of switches and diodes, such parameters as efficiency and volume of passive components in the multisection converter are analyzed in this paper. In figures, the analysis is demonstrated using the example of 100 kW thyristor-based converters. All the characteristics of the converter are compared between various configurations of switching cells in the particular sections, thus the paper can be useful for a design approach for a high voltage gain multicell converter.

Go to article

Authors and Affiliations

Stanisław Piróg
Robert Stala
Download PDF Download RIS Download Bibtex

Abstract

A novel circuit topology of modified switched boost high frequency hybrid resonant inverter fitted induction heating equipment is presented in this paper for efficient induction heating. Recently, induction heating technique is becoming very popular for both domestic and industrial purposes because of its high energy efficiency and controllability. Generally in induction heating, a high frequency alternating magnetic field is required to induce the eddy currents in the work piece. High frequency resonant inverters are incorporated in induction heating equipment which produce a high frequency alternating magnetic field surrounding the coil. Previously this high frequency alternating magnetic field was produced by voltage source inverters. But VSIs have several demerits. So, in this paper, a new scheme of modified switched boost high frequency hybrid resonant inverter fitted induction heating equipment has been depicted which enhances the energy efficiency and controllability and the same is validated by PSIM.

Go to article

Authors and Affiliations

Ananyo Bhattacharya
Kaushik Sit
Pradip Kumar Sadhu
Nitai Pal
Download PDF Download RIS Download Bibtex

Abstract

This paper presents a novel fault detection algorithm for a three-phase interleaved DC–DC boost converter integrated in a photovoltaic system. Interleaved DC–DC converters have been used widely due to their advantages in terms of efficiency, ripple reductions, modularity and small filter components. The fault detection algorithm depends on the input current waveform as a fault indicator and does not require any additional sensors in the system. To guarantee service continuity, a fault tolerant topology is achieved by connecting a redundant switch to the interleaved converter. The proposed fault detection algorithm is validated under different scenarios by the obtained results.
Go to article

Authors and Affiliations

Bilal Boudjellal
1
ORCID: ORCID
Tarak Benslimane
1
ORCID: ORCID

  1. Laboratory of Electrical Engineering, University of M’sila, Seat of the wilaya of M’sila, M’sila 28000, Algeria
Download PDF Download RIS Download Bibtex

Abstract

Food processing technologies for food preservation have been in constant development over a few decades in order to meet current consumer’s demands. Healthy competitive improvements are observed in both thermal and non-thermal food processing technology since past two decades due to technical revolution. Among these novel technologies, pulsed electric field food processing technology has shown to be a potential non-thermal treatment capable of preserving liquid foods. The high-voltage pulse generators specifically find their applications in pulsed electric field technology. So, this paper proposes a new structure of a high-voltage pulse generator with a cascaded boost converter topology. The choice of a cascaded boost converter helps in selecting low DC input voltage and hence the size and space requirement of the high-voltage pulse generator is minimized. The proposed circuit is capable of producing high-voltage pulses with flexibility of an adjusting duty ratio and frequency. The designed circuit generates a maximum peak voltage of 1 kV in the frequency range of 7.5–20 kHz and the pulse width range of 0.8–1.8 μs. Also, the impedance matching between the cascaded boost converter and the high-voltage pulse generator is found simple without further additional components. The efficiency can be improved in the circuit by avoiding low frequency transformers.
Go to article

Bibliography

[1] Nazni P., Shobana Devi R., Effect of Processing on the Characteristics Changes in Barnyard and Foxtail Millet, Journal of Food Processing Technology, vol. 7, no. 3, pp. 1–8 (2016).
[2] Khanam A., Platel K., Influence of domestic processing on the bioaccessibility of selenium from selected food grains and composite meals, Journal of Food Science and Technology, vol. 53, no. 3, pp. 1634–1639 (2016).
[3] Gabaza M., Shumoy H., Louwagie L., Muchuweti M., Vandamme P., Du Laing G., Raes K., Traditional fermentation and cooking of finger millet: Implications on mineral binders and subsequent bioaccessibility, Journal of Food Composition and Analysis, vol. 68, pp. 87–94 (2018).
[4] Sunil Neelash C., Jaivir S., Suresh C., Vipul C., Vikrant K., Non-thermal techniques: Application in food industries-A review, Journal of Pharmacognosy and Phytochemistry, vol. 7, no. 5, pp. 1507–1518 (2018).
[5] Nowosad K., Sujka M., Pankiewicz U., Kowalski R., The application of PEF technology in food processing and human nutrition, Journal of Food Science and Technology, vol. 58, pp. 397–411 (2020), DOI: 10.1007/s13197-020-04512-4.
[6] Rana Muhammad A., Xin-An Z., Zhong H., Amna S., Anees Ahmed K., Ubaid U.R., Muneeb K., Tariq M., Combined effects of pulsed electric field and ultrasound on bioactive compounds and microbial quality of grapefruit juice, Journal of Food Processing and Preservation, vol. 42, no. 2 (2018), DOI: 10.1111/jfpp.13507 (2018).
[7] Ramune B., Gianpiero P., Nerijus L., Saulius S., Pranas V., Giovanna F., Application of pulsed electric field in the production of juice and extraction of bioactive compounds from blueberry fruits and their by-products, Journal of Food Science and Technology, vol. 52, no. 9, pp. 5898–5905 (2015).
[8] Carbonell-Capella J.M., Buniowska M., Cortes C., Zulueta A., Frigola A., Esteve M.J., Influence of pulsed electric field processing on the quality of fruit juice beverages sweetened with Stevia rebaudiana, Food and Bioproducts Processing, vol. 101, pp. 214–222 (2017).
[9] Caminity I.M., Palgan I., Noci F., Arantxa Muñoz, Whyte P., Cronin D.A., Morgan D.J., Lyng J.G., The effect of pulsed electric fields (PEF) in combination with high intensity light pulses (HILP) on Escherichia coli inactivation and quality attributes in apple juice, Innovative Food Science and Emerging, vol. 12, no. 2, pp. 118–123 (2011).
[10] Morales-de la Pena M., Elez-Martinez P., Martin-Belloso O., Food Preservation by Pulsed Electric Fields: An Engineering Perspective, Food Engineering Reviews, vol. 3, pp. 94–107 (2011).
[11] Buckow R., Sieh N., Toepfl S., Pulsed electric field processing of orange juice: a review on microbial, enzymatic, nutritional and sensory quality and stability, Comprehensive Reviews in Food Science and Food safety, vol. 12, pp. 455–467 (2013).
[12] Toepfl S., Pulsed electric field food processing – Industrial equipment design and commercial applications, Stewart Postharvest Review, vol. 8, pp. 1–7 (2012).
[13] Valic B., Muriel Golzio, Mojca Pavlin, Anne Schatz, Cecile Faurie, Weaver J.C., Electroporation of Cells and Tissues, IEEE Transaction on Plasma Science, vol. 28, pp. 24–33 (2000).
[14] Toepfl S., Heinz V., Knorr D., High intensity pulsed electric fields applied for food preservation, Chemical Engineering and Processing, vol. 46, pp. 537–546 (2007).
[15] Geveke D.J., Kozempel M., Scullen O.J., Brunkhorst C., Radio frequency energy effects on microorganisms in foods, Innovative Food Science and Emerging Technology, vol. 3, no. 2, pp. 133–138 (2002).
[16] Geveke D.J., Brunkhorst C., Inactivation of Escherichia coli in apple juice by radio frequency electric fields, Journal of Food Science, vol. 69, pp. 134–138 (2004).
[17] Geveke D.J., Brunkhorst C., Fan X., Radio frequency electric fields processing of orange juice, Innovative Food Science and Emerging Technologies, vol. 8, pp. 549–554 (2007).
[18] Krishnaveni S., Rajini V., Diode clamped gate driver-based high voltage pulse generator for electroporation, Turkish Journal of Electrical Engineering and Computer Sciences, vol. 26, pp. 2374–2384 (2018).
[19] Pokryvailo A., Yankelevich Y., Shapira M., A compact source of sub gigawatt sub-nanosecond pulses, IEEE Transaction on Plasma Science, vol. 32, pp. 1909–1918 (2004).
[20] Wu Y., Liu K., Qiu J., X., Xiao H., Repetitive and high voltage Marx generator using solid-state devices, IEEE Transaction on Dielectrics and Electrical Insulation, vol. 14, pp. 937–940 (2007).
[21] Ramya R., Raja P.R., Gowrisree V., High Voltage Pulsed Electric Field Application Using Titanium Electrodes for Bacterial Inactivation in Unpurified Water, Japan Journal of Food Engineering, vol. 20, no. 2, pp. 63–70 (2019).
[22] KasriN.N.F., Piah M.A.M., Adzis Z., Compact High-Voltage Pulse Generator for Pulsed Electric Field Applications: Lab-Scale Development, Journal of Electrical and Computer Engineering, vol. 2020, art. ID 6525483, pp. 1–12 (2020), DOI: 10.1155/2020/6525483.
[23] Flisara K., Meglica S.H., Morelj J., Golobb J., Miklavcic D., Testing a prototype pulse generator for a continuous flow system and its use for E. coli inactivation and microalgae lipid extraction, Bioelectochemistry, vol. 100, pp. 44–51 (2014).
[24] Merensky L.M., Kardo-Sysoev A., Shmilovitz D., Kesar A.S., Efficiency Study of a 2.2 kV, 1 ns, 1 MHz Pulsed Power Generator Based on a Drift-Step-Recovery Diode, IEEE Transactions on Plasma Science, vol. 41, no. 11, pp. 3138–3142 (2013).
[25] Zhang Y., Liu J., Cheng X., Zhang H., Bai G., A Way for High-Voltage μs-Range Square Pulse Generation, IEEE Transactions on Plasma Science, vol. 39, no. 4, pp. 1125–1130 (2011).
[26] Merla C., Amari S.E., Kenaan M., Liberti M., Apollonio F., Arnaud-Cormos D., Couder V., A 10- High-Voltage Nanosecond Pulse Generator, IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 12, pp. 4079–4085 (2010).
[27] Ndtoungou A., Hamadi A., Missanda A., Al-Haddad K., Modeling and control of a cascaded Boost Converter for a Battery Electric Vehicle, IEEE Electrical Power and Energy Conference, London, ON, Canada, pp. 182–187 (2012).
[28] Stala R., Pirog S., DC–DC boost converter with high voltage gain and a low number of switches in multisection switched capacitor topology, Archives of Electrical Engineering, vol. 67, no. 3, pp. 617–627 (2018), DOI: 10.24425/123667.
[29] Chen Z., Yong W., Gao W., PI and Sliding Mode Control of a Multi-Input-Multi-Output Boost-Boost Converter, WSEAS Transactions on Power Systems, vol. 9, pp. 87–102 (2014).
[30] Sira-Ramirez H., Silva-Origoza R., Control design techniques in power electronics devices, Springer (2006).
[31] Aamir M., Shinwari M.Y., Design, implementation and experimental analysis of two-stage boost converter for grid connected photovoltaic system, 3rd IEEE International Conference on Computer Science and Information Technology, Chengdu, China, pp. 194–199 (2010).
[32] Park S., Choi S., Soft-switched CCM boost converters with high voltage gain for high power applications, IEEE Transaction on Power Electronics, vol. 25, no. 5, pp. 1211–1217 (2010).
[33] Silveira G.C., Tofoli F.L., Bezerra L.D.S., Torrico-Bascope R.P., A nonisolated DC-DC boost converter with high voltage gain and balanced output voltage, IEEE Transaction on Industrial Electronics, vol. 61, no. 12, pp. 6739–6746 (2014).
[34] Sanders J.M., Kuthi A., Wu., Y.H., Vernier P.T., Gundersen M.A., A linear, single-stage, nanosecond pulse generator for delivering intense electric fields to biological loads, IEEE Transactions on Dielectrics and Electrical Insulation, vol. 16, no. 4, pp. 1048–1054 (2009).


Go to article

Authors and Affiliations

S. Krishnaveni
1
ORCID: ORCID
V. Rajini
1

  1. Sri Sivasubramaniya Nadar College of Engineering, India
Download PDF Download RIS Download Bibtex

Abstract

The low frequency ripple of the input side current of the single-phase inverter will reduce the efficiency of the power generation system and affect the overall performance of the system. Aiming at this problem, this paper proposes a two-modal modulation method and its MPC multi-loop composite control strategy on the circuit topology of a single-stage boost inverter with a buffer unit. The control strategy achieves the balance of active power on both sides of AC and DC by controlling the stable average value of the buffer capacitor voltage, and provides a current reference for inductance current of the DC input side. At the same time, the MPC controller uses the minimum inductor current error as the cost function to control inductor current to track its reference to achieve low frequency ripple suppression of the input current. In principle, it is expounded that the inverter using the proposed control strategy has better low frequency ripple suppression effect than the multi-loop PI control strategy, and the conclusion is proved by the simulation data. Finally, an experimental device of a single-stage boost inverter using MPC multi-loop composite control strategy is designed and fabricated, and the experimental results show that the proposed research scheme has good low frequency ripple suppression effect and strong adaptability to different types of loads.
Go to article

Authors and Affiliations

Haiyang Liu
1
Yiwen Chen
1
Sixu Luo
1
ORCID: ORCID
Jiahui Jiang
2
ORCID: ORCID
Haojun Jian
3

  1. Fujian Key Laboratory of New Energy Generation and Power Conversion, Fuzhou University, China
  2. College of Electrical Engineering, Qingdao University, China
  3. State Grid Fujian Electric Power Co., Ltd. China
Download PDF Download RIS Download Bibtex

Abstract

The purpose of the article is a comparison between DC/DC topologies with a wide input voltage range. The research also explains how the implementation of GaN E‑HEMT transistors influences the overall efficiency of the converter. The article presents a process of selection of the most efficient topology for stabilization of the battery storage voltage (9 V – 36 V) at the level of 24 V, which enables the usage of ultracapacitor energy storage in a wide range of applications, e.g., in automated electric vehicles. In order to choose the most suitable topology, simulation and laboratory research were conducted. The two most promising topologies were selected for verification in the experimental model. Each of the converters was constructed in two versions: with Si and with GaN E-HEMT transistors. The paper presents experimental research results that consist of precise power loss measurements and thermal analysis. The performance with an increased switching frequency of converters was also examined.
Go to article

Bibliography

[1] M. Nowak and R. Barlik, „Poradnik inżyniera energoelektronika,” in WNT, Warszawa, pp.161-194, 1998. (in Polish)
[2] N. Mohan, W. P. Robbins, T. M. Undeland, and N. Mohan, “Solutions manual: power electronics: converters, applications, and design,” New York: Wiley, 1989.
[3] L. Wuidart, “Topologies For Switched Mode Power Supplies,” STMicroelectronics, 1999.
[4] M. Zehendner and M. Ulmann, “Power Topologies Handbook,” Texas Instrument, pp.23-171, 2016.
[5] X. Weng, X. Xiao, W. He, Y. Zhou, Y. Shen, W. Zhao, and Z. Zhao, "Comprehensive comparison and analysis of non-inverting buck boost and conventional buck boost converters" The Journal of Engineering, vol. 2019, no. 16, pp. 3030–3034, 2019. DOI: 10.1049/joe.2018.8373
[6] M. Luthfansyah, S. Suyanto, and A. Bakarr Momodu Bangura, "Evaluation and Comparison of DC-DC Power Converter Variations in Solar Panel Systems Using Maximum Power Point Tracking (MPPT) Flower Pollination Algorithm (FPA) Control" E3S Web of Conferences, vol. 190, p. 00026, 2020. DOI: 10.1051/e3sconf/202019000026
[7] B. Amri and M. Ashari, "The comparative study of Buck-boost, Cuk, Sepic and Zeta converters for maximum power point tracking photovoltaic using P&O method" 2015 2nd International Conference on Information Technology, Computer, and Electrical Engineering (ICITACEE), pp. 327-332, 2015. DOI: 10.1109/ICITACEE.2015.7437823
[8] M. V. D. de Sá and R. L. Andersen, "Dynamic modeling and design of a Cúk converter applied to energy storage systems" 2015 IEEE 13th Brazilian Power Electronics Conference and 1st Southern Power Electronics Conference (COBEP/SPEC), pp. 1-6. DOI: 10.1109/COBEP.2015.7420080, 2015
[9] B. M. M. Mwinyiwiwa and J. Dunia, "Performance Comparison between ĆUK and SEPIC Converters for Maximum Power Point Tracking Using Incremental Conductance Technique in Solar Power Applications," World Academy of Science, Engineering and Technology International Journal of Computer and Systems Engineering , vol. 7, no. 12. DOI: 10.5281/zenodo.1089293, 2013.
[10] Y. Attia and M. Youssef, "GaN on silicon E-HEMT and pure silicon MOSFET in high frequency switching of EV DC/DC converter: A comparative study in a nissan leaf," 2016 IEEE International Telecommunications Energy Conference (INTELEC), pp. 1-6, 2016. DOI: 10.1109/INTLEC.2016.7749112
[11] S. K. Pullabhatla, P. B. Bobba, and S. Yadlapalli, "Comparison of GAN, SIC, SI Technology for High Frequency and High Efficiency Inverters," E3S Web of Conferences, vol. 184, p. 01012, 2020. DOI: 10.1051/e3sconf/202018401012
[12] A. Deihimi and M. E. Mahmoodieh, "Analysis and control of battery‐integrated dc/dc converters for renewable energy applications" IET Power Electronics, vol. 10, no. 14, pp. 1819–1831, 2017. DOI: 10.1049/iet-pel.2016.0832
[13] R. Nowakowski and N. Tang, "Efficiency of synchronous versus nonsynchronous buck converters, " Texas Instruments, 2009. [14] Gan Systems, “GS61008T datasheet, ”, 2021 online: www.gansystems.com (2021).
[15] Infineon, “IPP030N10N5 datasheet”, Rev.2.3,2016-10-03, 2021. online: www.infineon.com.
[16] P. Grzejszczak , A. Czaplicki , M. Szymczak , R. Barlik „The impact of snubber circuits on switching energy losses in high frequency converters” Przeglad Elektrotechniczny, vol. 96, no. 06, pp 93-97, 2020, (in Polish). DOI: 10.15199/48.2020.06.17
[17] GN012 Application Guide Design with GaN Enhancement Mode HEMT, , 2021 online: www.gansystems.com (2021).
[18] M. Koszel and P. Grzejszczak, "Power loss estimating in GaN E-HEMT based synchronous buck-boost converter," 2020 Progress in Applied Electrical Engineering (PAEE), 2020, pp. 1-6. DOI: 10.1109/PAEE50669.2020.9158576
[19] D. Craig, "Common misconceptions about the MOSFET body diode," GaN Systems, 23-Oct-2019. online: https://gansystems.com/newsroom/common-misconceptions-about-the-mosfet-body-diode/ (2021)
Go to article

Authors and Affiliations

Mikołaj Koszel
1
Piotr Grzejszczak
1
Bartosz Nowatkiewicz
2
Kornel Wolski
1

  1. Warsaw University of Technology, Institute of Control and Industrial Electronics, Poland
  2. Wibar Technology Ltd., Poland
Download PDF Download RIS Download Bibtex

Abstract

DC-DC converters are popular switch-mode electronic circuits used in power supply systems of many electronic devices. Designing such converters requires reliable computation methods and models of components contained in these converters, allowing for accurate and fast computations of their characteristics. In the paper, a new averaged model of a diodetransistor switch containing an IGBT is proposed. The form of the developed model is presented. Its accuracy is verified by comparing the computed characteristics of the boost converter with the characteristics computed in SPICE using a transient analysis and literature models of a diode and an IGBT. The obtained results of computations proved the usefulness of the proposed model.

Go to article

Authors and Affiliations

Paweł Górecki
Download PDF Download RIS Download Bibtex

Abstract

Nowadays, there is a need to increase the continuous usage of the power electronic converters like AC-DC, DC-DC, and DC-AC based on various applications like mobile charge controller and telecom base station. Also, for power stability control, these converters are utilized in the renewable energy system (RES). The output cannot be stable for a longer duration due to the inappropriate switching pulse and continued usage of the converter. For resolving the above issues, the soft-switching technique is implemented in the proposed system for controlling both converter and inverter for proper energy stabilization during the continuous operation of devices. The main objective of this work is to improve the solar power system using high voltage gain DC / DC converter. Similarly, an inverter delivers the continuous AC power to the grid system without any fluctuations. The revolutionary substantial transformative control (RSTC) technique has been employed to monitor and control the converters used in this system. The additional advantage of this system is battery-based energy management, which is only utilized under necessary conditions. During the initial stage, RSTC will track the solar power, and it compares with the reference voltage and produces the appropriate pulse to the converter switch. Based on the switching pulse, the full-bridge converter (FBC) will also enhance the DC voltage by providing the constant voltage for the grid-connected inverter system. Secondly, the proposed RSTC controller will be monitoring voltage amplitude and frequency of grid power system. If any variation appears due to source power fluctuation, the controller will recognize it and automatically vary the pulse width modulation (PWM) of an inverter and compensate the grid power. The design analysis and operating approaches of the proposed converter are verified by MATLAB / Simulink 2017b. The performance analysis has been done with various parameters like total harmonics distortion (THD), steady-state error and converter efficiency.
Go to article

Authors and Affiliations

S. Umamaheswari
1
R. Karthigaivel
1
G. Satheesh Kumar
2
N. Vengadachalam
3

  1. PSNA College of Engineering and Technology, Kothandaraman nagar, Dindigul – 624622 Tamil Nadu, India
  2. SSM Institute of Engineering and Technology, Dindigul-Palani Highway, Dindigul, Tamil Nadu - 624002 India
  3. Malla Reddy Engineering College for Women, Maisammaguda, Dhulapally, Secunderabad-500100 Telangana, India
Download PDF Download RIS Download Bibtex

Abstract

Artificial neural networks are widely employed as data mining methods by researchers across various fields, including rainfall-runoff (R-R) statistical modelling. To enhance the performance of these networks, deep learning (DL) neural networks have been developed to improve modelling accuracy. The present study aims to improve the effectiveness of DL networks in enhancing the performance of artificial neural networks via merging with the gradient boosting (GB) technique for daily runoff data forecasting in the river Amu Darya, Uzbekistan. The obtained results showed that the new hybrid proposed model performed exceptionally well, achieving a 16.67% improvement in determination coefficient ( R2) and a 23.18% reduction in root mean square error ( RMSE) during the training phase compared to the single DL model. Moreover, during the verification phase, the hybrid model displayed remarkable performance, demonstrating a 66.67% increase in R 2 and a 50% reduction in RMSE. Furthermore, the hybrid model outperformed the single GB model by a significant margin. During the training phase, the new model showed an 18.18% increase in R 2 and a 25% reduction in RMSE. In the verification phase, it improved by an impressive 75% in R 2 and a 33.33% reduction in RMSE compared to the single GB model. These findings highlight the potential of the hybrid DL-GB model in improving daily runoff data forecasting in the challenging hydrological context of the Amu Darya River basin in Uzbekistan.
Go to article

Authors and Affiliations

Barno S. Abdullaeva
1
ORCID: ORCID

  1. Tashkent State Pedagogical University, Faculty of Math and Physics, 27 Bunyodkor Ave, 100070, Tashkent, Uzbekistan
Download PDF Download RIS Download Bibtex

Abstract

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 megasamples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Go to article

Bibliography

[1] Y. Zhou, B. Xu and Y. Chiu, “A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC,” IEEE Journal of Solid-State Circuits 54, 8, 2207-2218, (2019). https://doi.org/10.1109/JSSC.2019.2915583.
[2] D. Oh, J. Kim, D. Jo, W. Kim, D. Chang and S. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” IEEE Journal of Solid-State Circuits 54, 1, 288- 297,(2019). https://doi.org/10.1109/JSSC.2018.2870554.
[3] A. Wu, J. Wu, and J. Huang, “Energy-efficient switching scheme for ultra-low voltage SAR ADC.”, Analog Integr Circ Sig Process 90, 507–511, (2017). https://doi.org/10.1007/s10470-016-0892-0
[4] M. Guo, J. Mao, S. Sin, H. Wei and R. P. Martins, “A 1.6- GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration,”IEEE Journal of Solid-State Circuits 55, 3,693-705, (2020). https://doi.org/10.1109/JSSC.2019.2945298.
[5] M. Davidovic, G. Zach, H. Zimmermann, “An 11-bit successive approximation analog-to-digital converter based on a combined capacitor-resistor network.”, Elektrotech. Inftech. 127, 98–102, (2010). https://doi.org/10.1007/s00502-010-0704-7
[6] D. Chang, W. Kim, M. Seo, H. Hong, and S. Ryu, “Normalized- Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.”, IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, 322-332 (2017). https://doi.org/10.1109/TCSI.2016.2612692
[7] M. Shim et al.,“Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC”, IEEE Journal of Solid-State Circuits 52, 4, 1077-1090, (2017). https://doi.org/10.1109/JSSC.2016.2631299
[8] D. Zhang and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs 63, 3, 244-248, (2016). https://doi.org/10.1109/TCSII.2015.2482618.
[9] S.A. Zahrai, M. Onabajo, “ Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power- Efficient Hybrid Data Converters.”, J. Low Power Electron. Appl. 8, 12, (2018). https://doi.org/10.3390/jlpea8020012
[10] S.Taheri, J. Lin, J. S. Yuan,“Security Interrogation and Defense for SAR Analog to Digital Converter.”, Electronics 6, 48, (2017). https://doi.org/10.3390/electronics6020048
[11] J. Kim, B. Sung, W. Kim and S. Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS”, IEEE Journal of Solid-State Circuits 48, 6, 1429-1441, (2013). https://doi.org/10.1109/JSSC.2013.2252516
[12] S. Danesh, J. Hurwitz, K. Findlater, D. Renshaw and R. Henderson, “A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design”, IEEE Journal of Solid-State Circuits 48, 3, 733-748, (2013). https://doi.org/10.1109/JSSC.2013.2237672
[13] L. Wang, M. LaCroix and A. C. Carusone, “A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.”, IEEE Transactions on Circuits and Systems II: Express Briefs 64, 12, 1367-1371, (2017). https://doi.org/10.1109/TCSII.2017.2726063
[14] F. M´arquez, et al., “A novel autozeroing technique for flash Analog-to-Digital converters.”, Integration 47, 1, 23-29, (2014). https://doi.org/10.1016/j.vlsi.2013.06.002
[15] Masumeh Damghanian, Seyed Javad Azhari, “A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications.”, Integration 57, 158-168, (2017). https://doi.org/10.1016/j.vlsi.2017.01.006
[16] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan and J. J. Liou, “A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage,” IEEE Access 7, 93396- 93403,(2019). https://doi.org/10.1109/ACCESS.2019.2927514.
[17] A. Khatak, M. Kumar, S. Dhull, “An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits.”, J. Low Power Electron. Appl. 8, 33, (2018). https://doi.org/10.3390/jlpea8040033.
[18] B. Hershberg et al., “3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA 68-70, (2019). https://doi.org/10.1109/ISSCC.2019.8662319.
[19] U. Chio et al., “Design and Experimental Verification of a Power Effective Flash-SAR Sub ranging ADC.”, IEEE Transactions on Circuits and Systems II: Express Briefs 57, 8, 607-611, (2010). https://doi.org/10.1109/TCSII.2010.2050937
[20] Young-Deuk Jeon et al., “A dual-channel pipelined ADC with sub-ADC based on flash-SAR architecture.”, Circuits and Systems II: Express Briefs 59, 741-745. (2012). https://doi.org/10.1109/TCSII.2012.2222837
[21] Y. Lin et al.,“ A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.”, IEEE Transactions on Circuits and Systems I: Regular Papers 60, 3, 570-581, (2013). https://doi.org/10.1109/TCSI.2012.2215756
[22] J.I. Lee, J. Song, “Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count.”, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) 1-4, (2013). https://doi.org/10.1109/TENCON.2013.6718487
[23] A. Esmailiyan, F. Schembari and R. B. Staszewski, “A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump- Based Comparators in 28-nm CMOS,”IEEE Transactions on Circuits and Systems I: Regular Papers 67, 6, 1789-1802, (2020). https://doi.org/10.1109/TCSI.2020.2969804.
[24] J. Xu, et al., “Low-leakage analog switches for low-speed sample-and-hold circuits”, Microelectronics Journal 76, 22–27, (2018). https://doi.org/10.1016/j.mejo.2018.04.008
[25] M. Nazari, L. Sharifi,A. Aghajani, and O. Hashemipour, “A 12-bit high performance current-steering DAC using a new binary to thermometer decoder.”, 2016 24 Iranian Conference on Electrical Engineering (ICEE), Shiraz 2016 1919-1924, (2016). https://doi.org/10.1109/IranianCEE.2016.7585835
[26] H.S. Bindra et al., “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.”, IEEE Journal of Solid-State Circuits 53, 7, 1902-1912, (2018). https://doi.org/10.1109/JSSC.2018.2820147
[27] A. Taghizadeh, Z.D. Koozehkanani, J. Sobhi, “A new high-speed lowpower and low-offset dynamic comparator with a current-mode offset compensation technique.”, AEU - Int. J. Electron. Commun. 81, 163–170, (2018). https://doi.org/10.1016/j.aeue.2017.07.018.
[28] M. Saberi and R. Lotfi,“ Segmented Architecture for Successive Approximation Analog-to-Digital Converters.”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 3, 593-606, (2014). https://doi.org/10.1109/TVLSI.2013.2246592
[29] Y. Haga et al., “Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique.”, 2005 IEEE International Symposium on Circuits and Systems 1, 220-223, (2005). https://doi.org/10.1109/ISCAS.2005.1464564.
[30] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone- Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits 54, 3, 646-658, (2019). https://doi.org/10.1109/JSSC.2018.2889680.
[31] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC,” IEEE Journal of Solid-State Circuits 50, 12, 2901-2911, (2015). https://doi.org/10.1109/JSSC.2015.2463094
[32] B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.”, IEEE Communications Magazine 54, 4, 78-83, (2016). https://doi.org/10.1109/MCOM.2016.7452270
[33] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur196-199, (2010). https://doi.org/10.1109/APCCAS.2010.5774747.
[34] M. Hotta et al., “SAR ADC Architecture with Digital Error Correction.”. IEEJ Trans Elec Electron Eng 5, 651-659, (2010). https://doi.org/10.1002/tee.20588
[35] S. Lee, A.P. Chandrakasan and H. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC with Background Timing Skew Calibration.”, IEEE Journal of Solid-State Circuits 49, 12, 2846-2856, (2014). https://doi.org/10.1109/JSSC.2014.2362851
[36] M. Damghanian and S.J. Azhari, “A novel three-section encoder in a low-power 2.3 GS/s flash ADC.”, Microelectronics J 82, 71–80, (2018). https://doi.org/10.1016/j.mejo.2018.10.009
[37] Yi. Shen and Z. Zhu, “Analysis and optimization of the twostage pipelined SAR ADCs.”, Microelectronics Journal 47, 1–5, (2016). https://doi.org/10.1016/j.mejo.2015.10.018.
[38] Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu,“A 10-bit 100-MS/s 5.23 mW SAR ADC in 0.18 μm CMOS.”,Microelectronics Journal 78, 63-72, (2018). https://doi.org/10.1016/j.mejo.2018.06.007
[39] X. Xin et al.,“A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip.”,Microelectronics Journal 83, 104–116, (2019). https://doi.org/10.1016/j.mejo.2018.11.017
[40] W. Guo, S. Liu, and Z. Zhu, “ An asynchronous 12-bit 50MS/s rail-torail Pipeline-SAR ADC in 0.18 μm CMOS.”, Microelectronics Journal 52, 23–30, (2016). https://doi.org/10.1016/j.mejo.2016.03.003
[41] B. Samadpoor Rikan et al.,“A 10-bit 1 MS / s segmented Dual-Sampling SAR ADC with reduced switching energy.”, Microelectronics Journal 70, 89–96, (2017). https://doi.org/10.1016/j.mejo.2017.11.005
Go to article

Authors and Affiliations

Anil Khatak
1
ORCID: ORCID
Manoj Kumar
2
Sanjeev Dhull
3

  1. Faculty of Biomedical Engineering, GJUS&T, Hisar, Haryana, India
  2. Faculty of USICT, Guru Gobind Singh Indraprastha University, New Delhi, India
  3. Faculty of ECE, GJUS&T, Hisar, Haryana, India

This page uses 'cookies'. Learn more