This paper is devoted to multiple soft fault diagnosis of analog nonlinear circuits. A two-stage algorithm is offered enabling us to locate the faulty circuit components and evaluate their values, considering the component tolerances. At first a preliminary diagnostic procedure is performed, under the assumption that the non-faulty components have nominal values, leading to approximate and tentative results. Then, they are corrected, taking into account the fact that the non-faulty components can assume arbitrary values within their tolerance ranges. This stage of the algorithm is carried out using the linear programming method. As a result some ranges are obtained including possible values of the faulty components. The proposed approach is illustrated with two numerical examples.

This paper deals with multiple soft fault diagnosis of nonlinear analog circuits comprising bipolar transistors characterized by the Ebers-Moll model. Resistances of the circuit and beta forward factor of a transistor are considered as potentially faulty parameters. The proposed diagnostic method exploits a strongly nonlinear set of algebraic type equations, which may possess multiple solutions, and is capable of finding different sets of the parameters values which meet the diagnostic test. The equations are written on the basis of node analysis and include DC voltages measured at accessible nodes, as well as some measured currents. The unknown variables are node voltages and the parameters which are considered as potentially faulty. The number of these parameters is larger than the number of the accessible nodes. To solve the set of equations the block relaxation method is used with different assignments of the variables to the blocks. Next, the solutions are corrected using the Newton-Raphson algorithm. As a result, one or more sets of the parameters values which satisfy the diagnostic test are obtained. The proposed approach is illustrated with a numerical example.

In this paper we discuss some physical limits for scaling of transistors and conducting paths inside of semiconductor integrated circuits (ICs). Since 40 years only a semiconductor technology, mostly the CMOS and the TTL technologies, are used for fabrication of integrated circuits on an industrial scale. Miniaturization of electronic devices in integrated circuits has technological limits and physical limits as well. In 2010 best parameters of commercial ICs shown the Intel Core i5-670 processor manufactured in the technology of 32 nm. Its clock frequency in turbo mode is 3.73 GHz. A forecast of the development of the semiconductor industry (ITRS 2011) predicts that sizes of electronic devices in ICs circuits will be smaller than 10 nm in the next 10 years. At least 5 physical effects should be taken into account if we discuss limits of scaling of integrated circuits.

Electrical circuits with state-feedbacks are addressed. It is shown that by suitable choice of the gain matrices of state-feedbacks it is possible to obtain the closed-loop system matrices with nilpotency indices equal to two and their state variables are linear functions of time. The considerations are illustrated by linear electrical circuits.

The paper presents the results of a numerical study devoted to the hydraulic properties of a network of parallel triangular microchannels (hydraulic diameter Dh = 110 um). Previous experimental investigations had revealed that pressure drop through the microchannels system dramatically increases for the Reynolds number exceeding value of 10. The disagreement of the experimental findings with the estimations of flow resistance based on the assumption of fully developed flow were suspected to result from the so-called scale effect. Numerical simulations were performed by using the classical system of flow equations (continuity and Navier-Stokes equations) in order to explain the observed discrepancies. The calculations showed a very good agreement with the experimental results proving that there is no scale effect for the microchannels considered, i.e. the relevance of the constitutive flow model applied was confirmed. It was also clearly indicated that the excessive pressure losses in the high Reynolds number range are due to the secondary flows and separations appearing in several regions of the microchannel system.

This paper presents novel approach to the Huffman’s asynchronous sequential circuit two valued Boolean switching system design. The algorithm is implemented as software using distributed, service oriented application model with means of the web service component design. It considers method implementation challenges, both towards Moore and Mealy structures with particular respect to the estimation of the Huffman’s minimization algorithm computational complexity. The paper provides implementation details, theoretical model estimation and experimental results that acknowledge the theoretical approach in practice. This paper also examine the multistep design process implementation and its problems inherent in web service based environment both for development and educational purposes.

A new 4-D dynamical system exhibiting chaos is introduced in this work. The proposed nonlinear plant with chaos has an unstable rest point and a line of rest points. Thus, the new nonlinear plant exhibits hidden attractors. A detailed dynamic analysis of the new nonlinear plant using bifurcation diagrams is described. Synchronization result of the new nonlinear plant with itself is achieved using Integral Sliding Mode Control (ISMC). Finally, a circuit model using MultiSim of the new 4-D nonlinear plant with chaos is carried out for practical use.

The paper presents an assessment of flotation efficiency in the separation of plastics from metals derived from printed circuit boards (PCBs). The PCBs were ground in a knife mill prior to flotation. The contact angles of various materials corresponding to the grains from ground PCBs were measured, and a series of flotation tests was carried out to obtain the best product. The impact of the following parameters were investigated: the reagent and its dose, the airflow rate through the flotation tank and the feed concentration. The highest efficiency of metal recovery from PCBs was achieved for Dimethoxy dipropyleneglycol at a concentration of 157 mg/dm3 and with an airflow of 200 dm3/h and a feed concentration of <50 g/dm3. In the hydrophilic product (concentrate), it was mainly Cu (40%) and Sn (7.8%) that were identified by means of XRF, but there were also trace amounts of precious metals such as Au (0.024%), Ag (0.5797%) and Pd (149 ppm). Impurities in the form of Si (5%), Ca (3.2) and Br (2.1) were also identified in this product. Small amounts of metals in their metallic form were identified in the hydrophobic product (waste), mainly Cu (2.3), Al (1.7) and Sn (1.1). As a result of the research, high recovery ratios were obtained for Cu (93%), Sn (84), Ag (83) and Au (69). The purity of obtained metal concentrate with this method was lower in comparison with the other methods of the recovery of metals from ground PCBs for the same feed, i.e. electrostatic or gravity separation. Also considering other factors such as the environmental impact of the flotation process, the number of facilities and their energy consumption, this process should not be used in the developed metal recovery technology. Using electrostatic separation for the same feed obtained much better results.

The main aim of the below presented work was to investigate the possibility of using impedance spectroscopy in the unpasteurized beer microbial contamination degree assessment. Advantages of the impedance spectroscopy method, a negligible number of similar published results as well as their practical aspect make the research important. Four different types of beerswere investigated whichwere unfit for consumption due to improper storage and were heavily microbiologically contaminated. Their impedance was measured in the frequency range from 0.1 Hz to 1 kHz before and after centrifugation. Based on the measured values, an innovative electrical equivalent circuit was proposed and the parameters of the circuit elements were fitted. The obtained results show significant differences (23 up to 35%) in the values of resistance modelling the diffusion phenomenon. Such large changes, resulting from the removal of biomass from the samples, prove the validity of impedance spectroscopy in the study of the properties of unpasteurized beer. According to the authors, it would be possible to use the proposed methodology during the production of beer.With some limitations, it should aid in the early detection of microbial contamination.

In this article we present a procedure that allows to synthesize optimal circuit representing any reversible function within reasonable size limits. The procedure allows to choose either the NCT or the MCT gate set and specify any number of ancillary qubits to be used in the circuit. We will explore efficacy of this procedure by synthesizing various sources of nonlinearity used in contemporary symmetric ciphers and draw conclusions about properties of those transformations in quantum setting. In particular we will try to synthesize optimal circuit representing ASCON cipher SBOX which recently won NIST competition for Lightweight Cryptography standard.

Along with the increase in the use of nonlinear electronic devices, e.g. personal computers, power tools and other electrical appliances, the requirements for uninterruptible power supplies are constantly growing. This paper proposes a method and deep analysis of results viable for checking how single-phase uninterruptible power supplies (UPSs) cope with nonlinear circuits under varying power loads in terms of electric energy quality.Various classes of single-phase UPS systems with different topologies were tested, for instance line-interactive and double conversion (online) single-phase UPS devices. Furthermore, measurements were carried out in view of a power source – loads were supplied both from a power grid and UPS built-in battery. Juxtaposition of the obtained results such as a THDU, THDI (Total Harmonic Distortion) percentage ratio of input/output voltage and current, a power factor and crest factor volume etc. of the tested UPS systems indicated major differences in their performance during laboratory tests.

Minimum energy control problem for the fractional positive electrical circuits is formulated and solved. Sufficient conditions for the existence of solution to the problem are established. A procedure for solving of the problem is proposed and illustrated by an example of fractional positive electrical circuit.

Hull consistency is a known technique to improve the efficiency of iterative interval methods for solving nonlinear systems describing steady-states in various circuits. Presently, hull consistency is checked in a scalar manner, i.e. successively for each equation of the nonlinear system with respect to a single variable. In the present poster, a new more general approach to implementing hull consistency is suggested which consists in treating simultaneously several equations with respect to the same number of variables.

Field programmable analog arrays (FPAA), thanks to their flexibility and reconfigurability, give the designers quite new possibilities in analog circuit design. The number of both academic projects on FPAA and applications of commercially available programmable devices is still growing. This paper explores the properties and parameters of two most popular FPAA circuits: the AnadigmVortex AN221E04 and AnadigmApex AN231E04 from the Anadigm company. The research conducted by the authors led to the discovery of some undocumented features of these devices. Several applications for audio processing were built and tested. The results show that these circuits can be used in medium-demanding audio applications. Thanks to dynamic reconfigurability, they also allow to build an universal analog audio signal processor. These circuits can also act as a versatile platform for rapid prototyping and educational purposes.

In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

A measurement system for 256-channel in vitro recordings of brain tissue electrophysiological activity is presented in the paper. The system consists of the brain tissue life support system, Microelectrode Array (MEA), conditioning Application Specific Integrated Circuits (ASIC’s) for signals conditioning, Digitizer and PC application for measurement data presentation and storage. The life support system keeps brain tissue samples in appropriately saturated artificial cerebrospinal fluid at a very stable temperature. The MEA consists of two hundred and fifty-six 40 μm diameter tip-shaped electrodes. The ASIC’s performs amplification and filtering of the 256-field and action potential signals. The Digitizer performs simultaneous data acquisition from 256 channels 14 kS/s sample rate and 12-bit resolution. The resulting byte stream is transmitted to the PC via USB (Universal Serial Bus). Preliminary tests confirm that the system is capable of keeping the extracted brain tissue active (hippocampal formation slices) and simultaneously to record action potentials, as well as local theta field potentials with very small amplitudes from multiple neurons

The paper deals with fault diagnosis of nonlinear analogue integrated circuits. Soft spot short defects are analysed taking into account variations of the circuit parameters due to physical imperfections as well as self-heating of the chip. A method enabling to detect, locate and estimate the value of a spot defect has been developed. For this purpose an appropriate objective function was minimized using an optimization procedure based on the Fibonacci method. The proposed approach exploits DC measurements in the test phase, performed at a limited number of accessible points. For illustration three numerical examples are given.

The paper deals with multiple soft fault diagnosis of analogue circuits. A method for diagnosis of linear circuits is developed, belonging to the class of the fault verification techniques. The method employs a measurement test performed in the frequency domain, leading to the nonlinear least squares problem. To solve this problem the Powell minimization method is applied. The diagnostic method is adapted to real circumstances, taking into account deviations of fault-free parameters and measurement uncertainty. Two examples of electronic circuits encountered in practice demonstrate that the method is efficient for diagnosis of middle-sized circuits. Although the method is dedicated to linear circuits it can be adapted to multiple soft fault diagnosis of nonlinear ones. It is illustrated by an example of a CMOS circuit designed in a sub-micrometre technology.

One of the main problems of electrical power quality is to ensure a constant power ?ux from the supply system to the receiver, keeping in the same time the undisturbed wave form of the current and voltage signals. Distortion of signals are caused by nonlinear or time varying receivers, voltage changes or power losses in a supply system. The wave-form of the voltage of the source may also be deformed. This study seeks the optimal current and voltage wave-form by means of an optimization criteria. The optimization problem is de?ned in Hilbert space and the special functionals are minimized. The source inner impedance operator is linear and time-varying. Some examples of calculations are presented.

In the paper an application of evolutionary algorithm to design and optimization of combinational digital circuits with respect to transistor count is presented. Multiple layer chromosomes increasing the algorithm efficiency are introduced. Four combinational circuits with truth tables chosen from literature are designed using proposed method. Obtained results are in many cases better than those obtained using other methods.

The paper deals with a multiple fault diagnosis of DC transistor circuits with limited accessible terminals for measurements. An algorithm for identifying faulty elements and evaluating their parameters is proposed. The method belongs to the category of simulation before test methods. The dictionary is generated on the basis of the families of characteristics expressing voltages at test nodes in terms of circuit parameters. To build the fault dictionary the n-dimensional surfaces are approximated by means of section-wise piecewise-linear functions (SPLF). The faulty parameters are identified using the patterns stored in the fault dictionary, the measured voltages at the test nodes and simple computations. The approach is described in detail for a double and triple fault diagnosis. Two numerical examples illustrate the proposed method.