For many years, a digital waveguide model is being used for sound propagation in the modeling of the vocal tract with the structured and uniform mesh of scattering junctions connected by same delay lines. There are many varieties in the formation and layouts of the mesh grid called topologies. Current novel work has been dedicated to the mesh of two-dimensional digital waveguide models of sound propagation in the vocal tract with the structured and non-uniform rectilinear grid in orientation. In this work, there are two types of delay lines: one is called a smaller-delay line and other is called a larger-delay line. The larger-delay lines are the double of the smaller delay lines. The scheme of using the combination of both smaller- and larger-delay lines generates the non-uniform rectilinear two-dimensional waveguide mesh. The advantage of this approach is the ability to get a transfer function without fractional delay. This eliminates the need to get interpolation for the approximation of fractional delay and give efficient simulation for sound wave propagation in the two-dimensional waveguide modeling of the vocal tract. The simulation has been performed by considering the vowels /ɔ/, /a/, /i/ and /u/ in this work. By keeping the same sampling frequency, the standard two-dimensional waveguide model with uniform mesh is considered as our benchmark model. The results and efficiency of the proposed model have compared with our benchmark model.

The paper deals with the issue of constructing delay lines on the basis of surface acoustic waves and their application to single-mode oscillators. As a result of a theoretical analysis concrete delay lines are proposed.

In the contribution, there is presented a theory of designing a symmetrical mismatched and matched delay line for a single-mode oscillator of electrical signals on the basis of which there were designed and fabricated acoustic-electronic components for sensors of non-electrical quantities.

From the experimental results it can be stated that all of six designed and fabricated delay lines can be effectively used in the construction of single-mode oscillators.

The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.

The aim of this publication is to design a procedure for the synthesis of an IDT (interdigital transducer) with diluted electrodes. The paper deals with the surface acoustic waves (SAW) and the theory of synthesis of the asymmetrical delay line with the interdigital transducer with diluted electrodes. The authors developed a theory, design, and implementation of the proposed design. They also measured signals. The authors analysed acoustoelectronic components with SAW: PLF 13, PLR 40, delay line with PAV 44 PLO. The presented applications have a potential practical use.

The paper describes the construction, operation and test results of three most popular interpolators from a viewpoint of time-interval (TI) measurement systems consisting of many tapped-delay lines (TDLs) and registering pulses of a wide-range changeable intensity. The comparison criteria include the maximum intensity of registered time stamps (TSs), the dependency of interpolator characteristic on the registered TSs’ intensity, the need of using either two counters or a mutually-complementing pair counter-register for extending a measurement range, the need of calculating offsets between TDL inputs and the dependency of a resolution increase on the number of used TDL segments. This work also contains conclusions about a range of applications, usefulness and methods of employing each described TI interpolator. The presented experimental results bring new facts that can be used by the designers who implement precise time delays in the field-programmable gate arrays (FPGA).

Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.

The paper deals with hardware solution of a fully digital dead-time generator. The circuit is applicable to the H-bridges based on any type of semiconductor switching devices including SiC, IGBT, Si-MOSFET and up-to-date GaN HEMTs. The generation of dead-times is ensured by commercially available silicon delay lines. High temperature stability is obtained by self-compensation of propagation delay of logic elements thanks to the symmetry of design topology. The circuit can be set-up to generate dead-times in the range from 10 ns to 500 ns. Longer dead-times are also available by simple cascading of the silicon delay lines. The key motivation for development of the circuit was unavailability of ready to use integrated solutions on the market. Moreover, contrary to the other solutions the proposed circuit is immune to prospective oscillations of an input PWM signal. The paper brings a detailed analysis of the circuit principle, results of the verification of a sample solution and an example of practical application as well.