A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a number of spectrograms simultaneously and to reconstruct a flow velocity profile.
The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost.
The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.
Blood glucose level monitoring and control is of utmost importance to millions of people who have been diagnosed with diabetes or similar illnesses. One of the conventional tests for measuring how the human body breaks down glucose is IVGTT, the Intravenous Glucose Tolerance Test. The difficulty of computing the models of glucose-insulin interaction presents an issue when attempting to implement them in embedded hardware. The Metabolic P (MP), contrary to other models, does not require solving differential equations to compute, thus it could be an effective modelling approach for real-time applications. The present paper proves that MP system methodology-based IVGTT implementation in the Field Programmable Gate Arrays (FPGA) technology is reasonably precise and sufficiently flexible to be used effectively in multi-user scenarios. Presentation of the state-of-the-art focuses on glucose-insulin interaction models, glucose monitoring systems and MP system implementation techniques. Methods for MP system computations and techniques for their implementation on FPGA, together with the original unified MP system implementation technique, have been presented in this paper. The results of an elaborate investigation into the IVGTT MP systems, as well as their single and unified MP implementation techniques have also been considered. It is shown that the techniques developed are applicable to all known IVGTT MP systems, and can achieve RMSE not higher than 15% using a word length of at least 32 bits. The novel MP system combined quality metrics and its pictorial representation allow the analysis of various implementation characteristics. Compared to the unified pipelined IVGTT MP system implementation technique, the developed unified combinational technique ensures a 2‒3 times higher speed.
Most systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.
The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.