@ARTICLE{Svarny_Jiri_Reliable_2020,
 author={Svarny, Jiri},
 volume={vol. 69},
 number={No 4},
 journal={Archives of Electrical Engineering},
 pages={781-792},
 howpublished={online},
 year={2020},
 publisher={Polish Academy of Sciences},
 abstract={The paper deals with hardware solution of a fully digital dead-time generator. The circuit is applicable to the H-bridges based on any type of semiconductor switching devices including SiC, IGBT, Si-MOSFET and up-to-date GaN HEMTs. The generation of dead-times is ensured by commercially available silicon delay lines. High temperature stability is obtained by self-compensation of propagation delay of logic elements thanks to the symmetry of design topology. The circuit can be set-up to generate dead-times in the range from 10 ns to 500 ns. Longer dead-times are also available by simple cascading of the silicon delay lines. The key motivation for development of the circuit was unavailability of ready to use integrated solutions on the market. Moreover, contrary to the other solutions the proposed circuit is immune to prospective oscillations of an input PWM signal. The paper brings a detailed analysis of the circuit principle, results of the verification of a sample solution and an example of practical application as well.},
 type={Article},
 title={Reliable digital dead-time generator for the GaN HEMTs based H-bridge converters},
 URL={http://journals.pan.pl/Content/117662/PDF/art03.pdf},
 doi={10.24425/aee.2020.134629},
 keywords={dead-time generator, delay-line, GaN HEMTs, H-bridge driver},
}