@ARTICLE{Tabassum_Huma_ADC_2023,
 author={Tabassum, Huma and Prathik BV, Krishna and Hiremath, Sujatha S},
 volume={vol. 69},
 number={No 3},
 journal={International Journal of Electronics and Telecommunications},
 pages={425-430},
 howpublished={online},
 year={2023},
 publisher={Polish Academy of Sciences Committee of Electronics and Telecommunications},
 abstract={Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12/10/8/6 bit.},
 type={Article},
 title={ADC Emulation on FPGA},
 URL={http://journals.pan.pl/Content/128278/PDF/2-4202-Tabassum-sk1.pdf},
 doi={10.24425/ijet.2023.144379},
 keywords={ADC, resolution, FPGA, sampling, conversion},
}