@ARTICLE{Grzelak_Stanisław_HIGH_2014, author={Grzelak, Stanisław and Kowalski, Marcin and Czoków, Jarosław and Zieliński, Marek}, number={No 1}, journal={Metrology and Measurement Systems}, pages={77-84}, howpublished={online}, year={2014}, publisher={Polish Academy of Sciences Committee on Metrology and Scientific Instrumentation}, abstract={The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.}, type={Artykuły / Articles}, title={HIGH RESOLUTION TIME-INTERVAL MEASUREMENT SYSTEMS APPLIED TO FLOW MEASUREMENT}, URL={http://journals.pan.pl/Content/90222/PDF/Journal10178-VolumeXXI%20Issue1_08.pdf}, doi={10.2478/mms-2014-0008}, keywords={FPGA, time-to-digital converter, multi-segment delay line, carry chain}, }