TY - JOUR
N2 - Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
L1 - http://journals.pan.pl/Content/119412/PDF/29_01817_Bpast.No.69(2)_26.04.21_K1_G_TeX_OK.pdf
L2 - http://journals.pan.pl/Content/119412
PY - 2021
IS - 2
EP - e136728
DO - 10.24425/bpasts.2021.136728
KW - FPGA
KW - LUT
KW - Mealy FSM
KW - synthesis
KW - structural decomposition
KW - product terms
KW - partition
A1 - Barkalov, Alexander
A1 - Titarenko, Larysa
A1 - Mazurkiewicz, Małgorzata
A1 - Krzywicki, Kazimierz
VL - 69
DA - 08.03.2021
T1 - Improving LUT count of FPGA-based sequential blocks
SP - e136728
UR - http://journals.pan.pl/dlibra/publication/edition/119412
T2 - Bulletin of the Polish Academy of Sciences Technical Sciences
ER -