TY - JOUR N2 - The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described. L1 - http://journals.pan.pl/Content/90222/PDF/Journal10178-VolumeXXI%20Issue1_08.pdf L2 - http://journals.pan.pl/Content/90222 PY - 2014 IS - No 1 EP - 84 DO - 10.2478/mms-2014-0008 KW - FPGA KW - time-to-digital converter KW - multi-segment delay line KW - carry chain A1 - Grzelak, Stanisław A1 - Kowalski, Marcin A1 - Czoków, Jarosław A1 - Zieliński, Marek PB - Polish Academy of Sciences Committee on Metrology and Scientific Instrumentation DA - 2014 T1 - HIGH RESOLUTION TIME-INTERVAL MEASUREMENT SYSTEMS APPLIED TO FLOW MEASUREMENT SP - 77 UR - http://journals.pan.pl/dlibra/publication/edition/90222 T2 - Metrology and Measurement Systems ER -