Details Details PDF BIBTEX RIS Title A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process Journal title International Journal of Electronics and Telecommunications Yearbook 2010 Volume vol. 56 Numer No 4 Authors Zaziabl, Adam J. Divisions of PAS Nauki Techniczne Publisher Polish Academy of Sciences Committee of Electronics and Telecommunications Date 2010 Identifier DOI: 10.2478/v10177-010-0055-7 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012) References Gardner F. (2005), Phaselock techniques. ; Tierno J. (2008), A wide power supply range, wide tuning range, all static cmos all digital pll in 65 nm soi, IEEE Journal of Solid-State Circuits, 43, 42. ; Arakali A. (2008), Supply-noise mitigation techniques in phaselocked loops, null. ; Brownlee M. (2006), A 0.5-ghz to 2.5-ghz pll with fully differential supply regulated tuning, IEEE Journal of Solid-State Circuits, 41, 2720. ; Cao Z. (2008), A 0.4 ps-rms-jitter 13 ghz ring-oscillator pll using phase-noise preamplification, IEEE Journal of Solid-State Circuits, 43, 2079. ; Jung W. (2007), A 1.2mw 0.02mm2 2ghz current-controlled pll based on a self-biased voltage-to-current converter, null. ; Mansuri M. (2003), A low-power adaptive bandwidth pll and clock buffer with supply-noise compensation, IEEE Journal of Solid-State Circuits, 38, 1804. ; Yan G. (2005), A self-biased pll with current-mode filter for clock generation, null. ; Razavi B. (2001), Design of analog CMOS itegrated circuits. ; Baker J. (2005), CMOS circuit design, layout and simulation. ; Mansuri M. (2002), Fast frequency acquisition phasefrequency detectors for gsamples/s phase-locked loops, IEEE Journal of Solid-State Circuits, 37, 1331. ; Razavi B. (1996), Monolithic phase-locked loops and clock recovery circuits. ; Huang Q. (1996), Speed optimization of edge-triggered cmos circuits for gigaherz single-phase clocks, IEEE Journal of Solid-State Circuits, 31, 456. ; <i>Jitter measurements using SpecreRF</i>, Cadence Design Systems. ; A. Zaziabl, "Design of integrated phase-locked loop module in submicron process," Master's thesis, AGH University od Science and Technology, Cracow, Poland, June 2009.