Szczegóły Szczegóły PDF BIBTEX RIS Tytuł artykułu Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding Tytuł czasopisma International Journal of Electronics and Telecommunications Rocznik 2012 Wolumin vol. 58 Numer No 1 Autorzy Bukowiec, Arkadiusz Wydział PAN Nauki Techniczne Wydawca Polish Academy of Sciences Committee of Electronics and Telecommunications Data 2012 Identyfikator DOI: 10.2478/v10177-012-0005-7 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012) Źródło International Journal of Electronics and Telecommunications; 2012; vol. 58; No 1 Referencje Baranov S. (1994), Logic Synthesis for Control Automat, doi.org/10.1007/978-1-4615-2692-6 ; Barkalov A. (2009), Logic Synthesis for FSM-based Control Units, 53, doi.org/10.1007/978-3-642-04309-3 ; Salcic Z. (1998), VHDL and FPLDs in Digital Systems Design, Prototyping and Customization, doi.org/10.1007/978-1-4615-5827-9 ; Kubáatováa H. (2005), Design of Embedded Control Systems, 177. ; Jenkins J. (1994), Designing with FPGAs and CPLDs. ; Scholl C. (2001), Functional Decomposition with Application to FPGA Synthesis. ; Rawski M. (2005), Application of symbolic functional decomposition concept in FSM implementation targeting FPGA devices, null, 153. ; Borowik G. (2010), Efficient logic controller design, null. ; Adamski M. (2006), Architectural and Sequential Synthesis of Digital Devices. ; Bukowiec A. (2009), Structural decomposition of finite state machines, Electronics and Telecommunications Quarterly, 55, 2, 243. ; Bukowiec A. (2006), Synthesis of Mealy FSM with multiple shared encoding of microinstructions and internal states, null, 95. ; Bukowiec A. (2011), Architectural synthesis of FSMs with joined multiple encoding, Electrical Review, 2011, 11, 150. ; Bukowiec A. (2008), FSMs implementation into FPGAs with multiple encoding of states, null, 72. ; Moore E. (1956), Automata Studies, 34, 129. ; Mealy G. (1955), A method for synthesizing sequential circuits, Bell System Technical Journal, 34, 5, 1045. ; S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide. version 3.0." Microelectronics Center of North Carolina, Research Triangle Park, NC, Tech. Rep. 1991-IWLS-UG-Saeyang, 1991. [Online]. Available: <a target="_blank" href='http://jupiter3.csc.ncsu.edu/~brglez/Cite-BibFiles-Reprintshome/Cite-BibFiles-Reprints-Central/BibValidateCentralDB/Cite-ForWebPosting/1991-IWLSUG-Saeyang/1991-IWLSUGSaeyangguide.pdf'>http://jupiter3.csc.ncsu.edu/~brglez/Cite-BibFiles-Reprintshome/Cite-BibFiles-Reprints-Central/BibValidateCentralDB/Cite-ForWebPosting/1991-IWLSUG-Saeyang/1991-IWLSUGSaeyangguide.pdf</a> ; Bukowiec A. (2009), Synthesis of Finite State Machines for FPGA devices based on Architectural Decomposition, 13. ; Eles P. (1998), System Synthesis with VHDL, doi.org/10.1007/978-1-4757-2789-0 ; Thomas D. (2002), The Verilog Hardware Description Language.