Title

SMTBDD: New Form of BDD for Logic Synthesis

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2016

Volume

vol. 62

Issue

No 1

Authors

Kubica, Marcin ; Kania, Dariusz

Divisions of PAS

Nauki Techniczne

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2016

Identifier

DOI: 10.1515/eletel-2016-0004 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Source

International Journal of Electronics and Telecommunications; 2016; vol. 62; No 1

References

Yamashita (1998), and New Methods to Find Optimal Non - Disjoint Bi - Decompositions Design Proceedings of the ASP - DAC pp, Automation Conference, 98, 59. ; Scholl (2001), and : The Multiple Variable Order Problem for Binary Decision Diagrams : Theory and Practical Application : Design Proceedings of the ASPDAC pp, Automation Conference, 01. ; Opara (2010), Decomposition - based Logic Synthesis for PAL - based CPLDs of and No pp, International Journal Applied Mathematics Computer Science, 20, 367, doi.org/10.2478/v10006-010-0027-1 ; Roth (1962), Minimization Over Boolean Graphs of and Development pp, IBM Journal Research, 227, doi.org/10.1147/rd.62.0227 ; Rawski (1997), and Non - Disjoint Decomposition of Boolean Functions and Its Application in FPGA - oriented Technology Mapping Proceedings od the rd Conference pp, EUROMICRO, 24. ; Kania (2007), Logic synthesis for PAL - based CPLD - s based on two - stage decomposition The of Systems and Software vol pp, Journal, 80. ; Ochi (1991), and Breadth - First Manipulation of SBDD of Boolean Functions for Vector Processing th / Design pp, ACM IEEE Automation Conference, 28, 413. ; Akers (1978), Binary Decision Diagrams on Computers No pp, IEEE Transactions, 27, 509. ; Minato (1990), and Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean Function Manipulation th / Design pp, ACM IEEE Automation Conference, 27, 52, doi.org/10.1145/123186.123225 ; Legl (1996), nad A Boolean Approach to Performance - Directed Technology Mapping for LUT - Based FPGA Designs th Design pp, Automation Conference, 33, 730. ; Bryant (1986), Graph Based Algorithms for Boolean Function Manipulation on Computers vol no pp, IEEE Transactions, 35, 677.