Szczegóły

Tytuł artykułu

Improving LUT count of FPGA-based sequential blocks

Tytuł czasopisma

Bulletin of the Polish Academy of Sciences Technical Sciences

Rocznik

2021

Wolumin

69

Numer

2

Afiliacje

Barkalov, Alexander : University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland ; Barkalov, Alexander : Vasyl’ Stus Dohetsk National University, 21, 600-richya str., Vinytsia, 21021, Ukraine ; Titarenko, Larysa : University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland ; Titarenko, Larysa : Kharkiv National University of Radio Electronics, Nauky avenye, 14, 6166, Kharkiv, Ukraine ; Mazurkiewicz, Małgorzata : University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland ; Krzywicki, Kazimierz : The Jacob of Paradies University, ul. Teatralna 25, 66-400 Gorzów Wielkopolski, Poland

Autorzy

Słowa kluczowe

FPGA ; LUT ; Mealy FSM ; synthesis ; structural decomposition ; product terms ; partition

Wydział PAN

Nauki Techniczne

Zakres

e136728

Bibliografia

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Data

08.03.2021

Typ

Article

Identyfikator

DOI: 10.24425/bpasts.2021.136728 ; ISSN 2300-1917

Źródło

Bulletin of the Polish Academy of Sciences: Technical Sciences; 2021; 69; 2; e136728
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