Title

Build Testbenches for Verification in Shift Register ICs using SystemVerilog

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2022

Volume

vol. 68

Issue

No 3

Authors

Widianto ; Chasrun, H.M. ; Lis, Robert

Affiliation

Widianto : University of Muhammadiyah Malang, Department of Electrical Engineering, Indonesia ; Chasrun, H.M. : University of Muhammadiyah Malang, Department of Electrical Engineering, Indonesia ; Lis, Robert : Wroclaw University of Science and Technology, Poland

Keywords

testbench ; verification ; shift register IC ; stuck-atfaults ; SystemVerilog

Divisions of PAS

Nauki Techniczne

Coverage

619-623

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2022.09.06

Type

Article

Identifier

DOI: 10.24425/ijet.2022.141281