Title

Synthesis method of high speed finite state machines

Journal title

Bulletin of the Polish Academy of Sciences Technical Sciences

Yearbook

2010

Volume

58

Issue

No 4

Authors

Czerwiński, R. ; Kania, D.

Divisions of PAS

Nauki Techniczne

Coverage

635-644

Date

2010

Identifier

DOI: 10.2478/v10175-010-0067-6 ; ISSN 2300-1917

Source

Bulletin of the Polish Academy of Sciences: Technical Sciences; 2010; 58; No 4; 635-644

References

Anderson J. (1998), Technology mapping for large complex PLDs, Proc. Design Automation Conf, 1, 698. ; Kim J. (1999), Development of technology mapping algorithm for CPLD under time constraint, null, 1, 411. ; Kaviani A. (2000), Technology mapping issues for an fpga with lookup tables and pla-like blocks, null, 1, 60. ; Villa T. (1990), NOVA: state assignment for finite state machines for optimal two-level logic implementation, IEEE Trans. on Computer-Aided Design, 9, 905, doi.org/10.1109/43.59068 ; Sentovich E. (1992), SIS: a system for sequential circuit synthesis, ICCD, Proc. Int. Conf. Computer Design, 1, 328. ; Salauyou V. (2006), Investigation of efficiency of synthesis of finite automata implemented in the ZUBR packet, Measurements, Automatics, Control, 6, 44. ; Barkalov A. (2007), Reduction in the number of PAL macrocells in the circuit of a Moore FSM, Int. J. Applied Mathematics and Computer Science, 17, 4, 565, doi.org/10.2478/v10006-007-0046-8 ; Chattopadhyay S. (2001), Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach, IEE Proc. - Computers and Digital Techniques, 148, 45, 147, doi.org/10.1049/ip-cdt:20010666 ; Cao C. (2004), A tool for low-power synthesis of FSMs with mixed synchronous/asynchronous state memory, IEEE Norchip Conf, 1, 199, doi.org/10.1109/NORCHP.2004.1423857 ; Park S. (2000), Optimal state assignment technique for partial scan designs, Electronics Letters, 36, 18, 1527, doi.org/10.1049/el:20001086 ; Salauyou V. (2007), FSM state assignment methods for low-power design, null, 1, 345. ; Lala P. (1978), An algorithm for the state assignment of synchronous sequential circuits, Electronics Letters, 14, 6, 199, doi.org/10.1049/el:19780133 ; Kania D. (2004), The logic synthesis for programmable matrix structures of PAL type, null, 1619. ; Lin B. (1989), Synthesis of multiple level logic from symbolic high-level description languages, Proc. Int. Conf. on VLSI, 1, 187. ; MCNC, "LGSynth'91 benchmarks", <i>Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University</i> <a target="_blank" href='http://www.cbl.ncsu.edu/'>http://www.cbl.ncsu.edu/</a> ; R. Czerwiński, "The FSMs state assignment for PAL-based matrix programmable structures", <i>PhD Thesis</i>, Silesian University of Technology, Gliwice, 2006, (in Polish).