Tytuł artykułu

Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)

Tytuł czasopisma

International Journal of Electronics and Telecommunications

Rocznik

2025

Wolumin

vol. 71

Numer

No 2

Autorzy

Satyanarayana, D. ; Chennakesavulu, M. ; Fouzia Sulthana, N. ; Upendra, K. ; Sashidhar, D. ; Ramachandra Reddy, K. ; Naga Sai Vikranth, N. ; Devendra, V.

Afiliacje

Satyanarayana, D. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Chennakesavulu, M. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Fouzia Sulthana, N. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Upendra, K. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Sashidhar, D. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Ramachandra Reddy, K. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Naga Sai Vikranth, N. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India ; Devendra, V. : Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, India

Słowa kluczowe

Low power ; Full adder ; Multiplier ; Delay ; PassTransistor

Wydział PAN

Nauki Techniczne

Zakres

483-488

Wydawca

Polish Academy of Sciences Committee of Electronics and Telecommunications

Data

4.06.2025

Typ

Article

Identyfikator

DOI: 10.24425/ijet.2025.153595 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)