[1] P. Babighian, L. Benini, and E. Macii: A scalable algorithm for RTL insertion of gated clocks based onODCscomputation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(1), (2005), 29–42, DOI:
10.1109/TCAD.2004.839489.
[2] R. Bellman: Dynamic programming and stochastic control processes.
Information and Control, 1(3), (1958), 228–239, DOI:
10.1016/S0019- 9958(58)80003-0.
[3] L. Benini, P. Siegel, and G. De Micheli: Saving power by synthesizing gated clocks for sequential circuits.
IEEE Design & Test of Computers, 11(4), (1994), 32–41, DOI:
10.1109/54.329451.
[4] R. Bhutada and Y. Manoli: Complex clock gating with integrated clock gating logic cell. In
2007 International Conference on Design Technology of Integrated Systems in Nanoscale Era, (2007), 164–169, DOI:
10.1109/DTIS.2007.4449512.
[5] J. Billon:
Perfect normal forms for discrete programs. Technical report, Bull, 1987.
[6] E.M. Clarke, E.A. Emerson, and A.P. Sistla: Automatic verification of finite-state concurrent systems using temporal logic specifications.
ACM Transactions on Programming Languages and Systems, 8(2), (1986), 244– 263, DOI:
10.1145/5397.5399.
[7] E. Dumitrescu, A. Girault, H. Marchand, and E. Rutten: Multicriteria optimal reconfiguration of fault-tolerant real-time tasks.
IFAC Proceedings Volumes, 43(12), (2010), 356–363, DOI:
10.3182/20100830-3-DE- 4013.00059.
[8] K. Gilles: The semantics of a simple language for parallel programming.
Information Processing, 74 (1974), 471–475.
[9] E.A. Lee and T.M. Parks: Dataflow process networks.
Proceedings of the IEEE, 83(5), (1995), 773–801, DOI:
10.1109/5.381846.
[10] H. Marchand and M.L. Borgne: On the optimal control of polynomial dynamical systems over z/pz. In
4th International Workshop on Discrete Event Systems, (1998), 385–390.
[11] H. Marchand, P. Bournai, M.L. Borgne, and P.L. Guernic: Synthesis of discrete-event controllers based on the signal environment.
Discrete Event Dynamic System: Theory and Applications, 10(4), (2000), 325–346, DOI:
10.1023/A:1008311720696.
[12] S. Miremadi, B. Lennartson, and K. Akesson: A BDD-based approach for modeling plant and supervisor by extended finite automata.
IEEE Transactions on Control Systems Technology, 20(6), (2012), 1421–1435, DOI:
10.1109/TCST.2011.2167150.
[13] M. Özbaltan:
Achieving Power Efficiency in Hardware Circuits with Symbolic Discrete Control. PhD thesis, University of Liverpool, 2020.
[14] M. Özbaltan and N. Berthier: Exercising symbolic discrete control for designing low-power hardware circuits: an application to clock-gating.
IFAC-PapersOnLine, 51(7), (2018), 120–126, DOI:
10.1016/j.ifacol.2018.06.289.
[15] M. Özbaltan and N. Berthier: A case for symbolic limited optimal discrete control: Energy management in reactive data-flow circuits.
IFAC-PapersOnLine, 53(2), (2020), 10688–10694, DOI:
10.1016/j.ifacol. 2020.12.2842.
[16] M. Pedram and Q.Wu: Design considerations for battery-powered electronics. In
Proceedings 1999 Design Automation Conference, (1999), 861–866, DOI: 10.1109/DAC.1999.782166.
[17] N. Raghavan, V. Akella, and S. Bakshi: Automatic insertion of gated clocks at register transfer level. In
Proceedings of the 12th International Conference on VLSI Design, (1999), 48–54, DOI:
10.1109/ICVD.1999.745123.
[18] P. Ramadge and W. Wonham: The control of discrete event systems.
Proceedings of the IEEE, 77(1), (1989), 81–98, DOI:
10.1109/5.21072.
[19] S. Tripakis, R. Limaye, K. Ravindran, G. Wang, H. Andrade, and A. Ghosal: Tokens vs. signals: On conformance between formal models of dataflow and hardware.
Journal of Signal Processing Systems, 85(1), (2016), 23–43, DOI:
10.1007/s11265-015-0971-y.
en
pl
