Szczegóły
Tytuł artykułu
High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed ArithmeticTytuł czasopisma
International Journal of Electronics and TelecommunicationsRocznik
2021Wolumin
vol. 67Numer
No 4Autorzy
Afiliacje
Cheepurupalli, Kusma Kumari : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India ; Charan, Muntha : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India ; Rao, Jammu Bhaskara : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India ; Noor, Mahammad S. : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, IndiaSłowa kluczowe
Fast Fourier Transform ; Adders ; Distributed Arithmetic ; DSPWydział PAN
Nauki TechniczneZakres
631-637Wydawca
Polish Academy of Sciences Committee of Electronics and TelecommunicationsBibliografia
[1] H. Kim and S. Lekcharoen, “A cooley-tukey modified algorithm in fast fourier transform,” The Korean Journal of Mathematics, vol. 19, no. 3, 2011.[2] J. Watson, “Digital signal processing: Principles, devices and applications.” Institution of Electrical Engineers, 1990.
[3] B. Mohindroo, A. Paliwal, and K. Suneja, “Fpga based faster implementation of mac unit in residual number system,” in 2020 International Conference for Emerging Technology (INCET). IEEE, 2020, pp. 1–4.
[4] R. Gonzalez-Toral, P. Reviriego, J. A. Maestro, and Z. Gao, “A scheme to design concurrent error detection techniques for the fast fourier transform implemented in sram-based fpgas,” IEEE Transactions on Computers, vol. 67, no. 7, pp. 1039–1045, 2018.
[5] K. K. Parhi, VLSI digital signal processing systems: design and implementation. John Wiley & Sons, 2007.
[6] D. Deepak and R. D. Kiran, “Hardware implementation of discrete cosine transform,” 2002.
[7] R. Guo and L. S. DeBrunner, “A novel adaptive filter implementation scheme using distributed arithmetic,” in 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR). IEEE, 2011, pp. 160–164.
[8] S. Patel, “Design and implementation of 31-order fir low-pass filter using modified distributed arithmetic based on fpga,” International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 2, no. 10, pp. 650–656, 2013.
[9] S. Venkatachalam and S.-B. Ko, “Approximate sum-of-products designs based on distributed arithmetic,” IEEE Transactions on very large scale integration (VLSI) systems, vol. 26, no. 8, pp. 1604–1608, 2018.
[10] K. N. Bowlyn and N. M. Botros, “A novel distributed arithmetic multiplierless approach for computing complex inner products,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA). The Steering Committee of The World Congress in Computer Science, Computer , 2015, p. 606.
[11] E. E. Swartzlander and C. E. Lemonds, Computer Arithmetic: Volume III. World Scientific, 2015.
[12] K. Vitoroulis and A. J. Al-Khalili, “Performance of parallel prefix adders implemented with fpga technology,” in 2007 IEEE Northeast Workshop on Circuits and Systems. IEEE, 2007, pp. 498–501.
[13] A. K. Y. Reddy and S. P. Kumar, “Performance analysis of 8-point fft using approximate radix-8 booth multiplier,” in 2018 3rd International Conference on Communication and Electronics Systems (ICCES). IEEE, 2018, pp. 42–45.
[14] A. Ajay and R. M. Lourde, “Vlsi implementation of an improved multiplier for fft computation in biomedical applications,” in 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2015, pp. 68–73.
[15] N. M. Sk et al., “Multi-mode parallel and folded vlsi architectures for 1d-fast fourier transform,” Integration, vol. 55, pp. 43–56, 2016.