Title

High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2021

Volume

vol. 67

Issue

No 4

Affiliation

Cheepurupalli, Kusma Kumari : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India ; Charan, Muntha : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India ; Rao, Jammu Bhaskara : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India ; Noor, Mahammad S. : Dept. of ECE, Gayatri Vidya Parishad College of Engineering, India

Authors

Cheepurupalli, Kusma Kumari ; Charan, Muntha ; Rao, Jammu Bhaskara ; Noor, Mahammad S.

Keywords

Fast Fourier Transform ; Adders ; Distributed Arithmetic ; DSP

Divisions of PAS

Nauki Techniczne

Coverage

631-637

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Bibliography

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[11] E. E. Swartzlander and C. E. Lemonds, Computer Arithmetic: Volume III. World Scientific, 2015.
[12] K. Vitoroulis and A. J. Al-Khalili, “Performance of parallel prefix adders implemented with fpga technology,” in 2007 IEEE Northeast Workshop on Circuits and Systems. IEEE, 2007, pp. 498–501.
[13] A. K. Y. Reddy and S. P. Kumar, “Performance analysis of 8-point fft using approximate radix-8 booth multiplier,” in 2018 3rd International Conference on Communication and Electronics Systems (ICCES). IEEE, 2018, pp. 42–45.
[14] A. Ajay and R. M. Lourde, “Vlsi implementation of an improved multiplier for fft computation in biomedical applications,” in 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2015, pp. 68–73.
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Date

2021.12.27

Type

Article

Identifier

DOI: 10.24425/ijet.2021.137856