Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 2
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

A testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, environment, test, and testbench top. The IC consists of sequential logic circuits of D-type flip-flops. The faults may occur at interconnects between the circuits inside the IC. In order to examine the functionality from the faults, both the testbench and the IC are designed using SystemVerilog and simulated using Questasim simulator. Simulation results show the faults may be detected by the testbench. Moreover, the detected faults may be indicated by error statements in transcript results of the simulator.
Go to article

Authors and Affiliations

Widianto
1
H.M. Chasrun
1
Robert Lis
2
ORCID: ORCID

  1. University of Muhammadiyah Malang, Department of Electrical Engineering, Indonesia
  2. Wroclaw University of Science and Technology, Poland
Download PDF Download RIS Download Bibtex

Abstract

The paper presents a honey badger algorithm (HB) based on a modified backwardforward sweep power flow method to determine the optimal placement of droop-controlled dispatchable distributed generations (DDG) corresponding to their sizes in an autonomous microgrid (AMG). The objectives are to minimise active power loss while considering the reduction of reactive power loss and total bus voltage deviation, and the maximisation of the voltage stability index. The proposed HB algorithm has been tested on a modified IEEE 33-bus AMG under four scenarios of the load profile at 40%, 60%, 80%, and 100% of the rated load. The analysis of the results indicates that Scenario 4, where the HB algorithm is used to optimise droop gains, the positioning of DDGs, and their reference voltage magnitudes within a permissible range, is more effective in mitigating transmission line losses than the other scenarios. Specifically, the active and reactive power losses in Scenario 4 with the HB algorithm are only 0.184% and 0.271% of the total investigated load demands, respectively. Compared to the base scenario (rated load), Scenario 4 using the HB algorithm also reduces active and reactive power losses by 41.86% and 31.54%, respectively. Furthermore, the proposed HB algorithm outperforms the differential evolution algorithm when comparing power losses for scenarios at the total investigated load and the rated load. The results obtained demonstrate that the proposed algorithm is effective in reducing power losses for the problem of optimal placement and size of DDGs in the AMG.
Go to article

Authors and Affiliations

Tham X. Nguyen
1
ORCID: ORCID
Robert Lis
1
ORCID: ORCID

  1. Faculty of Electrical Engineering, Wrocław University of Science and Technology, Wybrzeze Wyspianskiego 27, 50-370 Wrocław, Poland

This page uses 'cookies'. Learn more