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Abstract

In order to solve the problem of misjudgment caused by the traditional power grid fault diagnosis methods, a new fusion diagnosis method is proposed based on the theory of multisource information fusion. In this method, the fault degree of the power element is deduced by using the Bayesian network. Then, the time-domain singular spectrum entropy, frequencydomain power spectrum entropy and wavelet packet energy spectrum entropy of the electrical signals of each circuit after the failure are extracted, and these three characteristic quantities are taken as the fault support degree of the power components. Finally, the four fault degrees are normalized and classified as four evidence bodies in the D-S evidence theory for multifeature fusion, which reduces the uncertainty brought by a single feature body. Simulation results show that the proposed method can obtain more reliable diagnosis results compared with the traditional methods.
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Bibliography

[1] Yao Yuantao, Wang Jin, Xie Min, Hu Liqin and Wang Jianye, ”A new approach for fault diagnosis with full-scope simulator based on state information imaging in nuclear power plant”, Annals of Nuclear Energy, 2020, 141, 1-9.
[2] Lei Koua, Chuang Liua, Guo-wei Caia, Zhe Zhangb, ”Fault Diagnosis for Power Electronics Converters based on Deep Feedforward Network and Wavelet Compression”, Electric Power Systems Research, 2020, 185, 1-9.
[3] Haibo Zhang, Kai Jia, Weijin Shi, Jianzhao Guo, Weizhi Su and Li Zhang, ”Power Grid Fault Diagnosis Based on Information Theory and Expert System”, Proceedings of the CSU-EPSA,, 2017, 29(8), 111-118.
[4] Jianfeng Zhou, Genserik Reniers and Laobing Zhang, ”A weighted fuzzy Petri-net based approach for security risk assessment in the chemical industry”, Chemical Engineering Science, 2017, 174, 136-145.
[5] Sen Wang and Xiaorun Li, ”Circuit Breaker Fault Detection Method Based on Bayesian Approach”, Industrial Control Computer, 2018, 31(4), 147-151.
[6] Kaikai Gu and Jiang Guo, ”Transformer Fault Diagnosis Method Based on Compact Fusion of Fuzzy Set and Fault Tree”, High Voltage Engineering , 2014, 40(05), 1507-1513.
[7] Jun Miao, Qikun Yuan, Liwen Liu, Zhipeng You and Zhang Wang, ”Research on robot circuit fault detection method based on dynamic Bayesian network”, Electronic Design Engineering, 2020, 28(9), 184- 188.
[8] Bangcheng Lai and Genxiu Wu, ”The Evidence Combination Method Based on Information Entropy”, Journal of Jiangxi Normal University (Natural Science), 2012, 36(5), 519-523.
[9] Libo Liu, Tingting Zhao, Yancang Li and Bin Wang, ”An Improved Whale Algorithm Based on Information Entry”, Mathematics in practice and theory, 2020, 50(2), 211-219.
[10] Juan Yan, Minfang Peng, et al., ”Fault Diagnosis of Grounding Grids Based on Information Entropy and Evidence Fusion”, Proceedings of the CSU-EPSA, 2017, 29(12),8-13.
[11] Ershadi, Mohammad Mahdi and Seifi, Abbas, ”An efficient Bayesian network for differential diagnosis using experts’ knowledge”, International Journal of Intelligent Computing and Cybernetics, 2020, 13(1), 103-126.
[12] Guan Li, Zhifeng Liu, Ligang Cai and Jun Yan, ”Standing-Posture Recognition in Human–Robot Collaboration Based on Deep Learning and the Dempster–Shafer Evidence Theory”, Sensors, 2020, 20(4), 1- 17.
[13] Xiaofei He, Xiaoyang Tong and Shu Zhou, ”Power system fault diagnosis based on Bayesian network and fault section location”, Power system protection and control, 2010, 38(12), 29-34.
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Authors and Affiliations

Xin Zeng
1 2
Xingzhong Xiong
1 3
Zhongqiang Luo
1 3

  1. School of Automation and Information Engineering, Sichuan University of Science and Engineering, Yibin, China
  2. Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, China
  3. Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan Universityof Science and Engineering, Yibin, China
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Abstract

The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second signals (PPS). The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication.
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Bibliography

1] M. Dong, Z. Qiu, W. Pan, C. Chen, J. Zhang and D. Zhang, "The Design and Implementation of IEEE 1588v2 Clock Synchronization System by Generating Hardware Timestamps in MAC Layer," 2018 International Conference on Computer, Information and Telecommunication Systems (CITS), Colmar, 2018, pp. 1-5.
[2] Chavan A., Nagurvalli S., Jain M., Chaudhari S. (2018) Implementation of FPGA-Based Network Synchronization Using IEEE 1588 Precision Time Protocol (PTP). In: Sa P., Bakshi S., Hatzilygeroudis I., Sahoo M. (eds) Recent Findings in Intelligent Computing Techniques. Advances in Intelligent Systems and Computing, vol 708. Springer, Singapore.
[3] R. Exel, T. Bigler and T. Sauter, "Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Syn chronization," in IEEE Transactions on Instrumentation and Measurement, vol. 63, no. 3, pp. 729- 736, March 2014.
[4] W. Tseng, S. Siu, S. Lin and C. Liao, "Precise UTC dissemination through future telecom synchronization networks," 2015 Joint Conference of the IEEE International Frequency Control Symposium & the European Frequency and Time Forum, Denver, CO, 2015, pp. 696-699.
[5] O. Ronen and M. Lipinski, "Enhanced synchronization accuracy in IEEE1588," 2015 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS), Beijing, 2015, pp. 76-81.
[6] IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Sys tems," in IEEE Std 1588-2008 (Revision of IEEE Std 1588-2002) , vol., no., pp.1-300, 24 July 2008.
[7] Eleftherios Kyriakakis, Jens Sparsø, and Martin Schoeberl. 2018. Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol. In Proceedings of the 26th International Conference on Real-Time Networks and Systems (RTNS ’18). Association for Computing Machinery, New York, NY, USA, 51–60.
[8] W.Jinqi, C.Hong, "Implementation of IEEE1588 Precision Clock Synchronization Protocol Based on ARM",2019,42(06):1527-1531.
[9] G. Giorgi and C. Narduzzi, "Performance Analysis of Kalman-Filter- Based Clock Synchronization in IEEE 1588 Networks," in IEEE Transactions on Instrumentation and Measurement, vol. 60, no. 8, pp. 2902-2909, Aug. 2011.
[10] Lee S. An enhanced IEEE 1588 time synchronization algorithm for asymmetric communication link using block burst transmission[J]. IEEE communications letters, 2008, 12(9): 687-689.
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[14] O. Seijo, I. Val, J. A. Lopez-Fernandez and M. Velez, "IEEE 1588 Clock Synchronization Performance over Time-Varying Wireless Channels," 2018 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS), Geneva, 2018, pp. 1-6.
[15] S. Lee and C. Hong, "An Accuracy Enhanced IEEE 1588 Synchronization Protocol for Dynamically Changing and Asymmetric Wireless Links," IEEE Communications Letters, vol. 16, no. 2, pp. 190-192, February 2012.
[16] The Linux PTP Project. [Online]. Available: http://linuxptp.sourceforge.net/, accessed Dec. 2015.
[17] N. Moreira, J. Lázaro, U. Bidarte, J. Jimenez, and A.Astarloa, "On the Utilization of System-on-Chip Platformsto Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems."
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Authors and Affiliations

Xiaohan Wei
1
Xingzhong Wei
1
Zhongqiang Luo
1
Jianwu Wang
1
Kaixing Cheng
1

  1. School of Automation and Information Engineering and Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, China
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Abstract

As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the ”spiral wiring” way and the ”double spiral wiring” way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs.
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Bibliography

[1] Gong Yonglin. The hot spots of printed circuit technology in 2020. Printed Circuit Information, 28(2):1–11, 2020.
[2] Myeonghoon Oh, Youngwoo Kim, Hag Young Kim, Young Kyun Kim, and Jinsung Kim. Wire optimization and delay reduction for highperformance on-chip interconnection in gals systems. Etri Journal, 39(4):582–591, 2017.
[3] YuanWei-Qun, Song Jian-Yuan, Chen Shi-Rong, Suntak Technology Co, and LTD. Research and optimization design of high-speed pcb based on signal integrity. Journal of Guangdong University of Technology, 36(6):74–79, 2019.
[4] L.W.; Zhao Z.L. Yang, C.Z.; De. Research on signal integrity in high speed digital pcb board design. Automation and Instrumentation, (9):1– 4, 2018.
[5] YuanWei-Qun, Song Jian-Yuan, Chen Shi-Rong, Suntak Technology Co, and LTD. Research and optimization design of high-speed pcb based on signal integrity. Journal of Guangdong University of Technology, 36(6):74–79, 2019.
[6] Zhang Min. Signal integrity and design optimization of high speed parallel bus interface. Wireless Internet Technology, 15(6):3–4, 2019.
[7] Nastaran Soleimani, Mohammad G H Alijani, and Mohammad Hassan Neshati. Crosstalk analysis of multi-microstrip coupled lines using transmission line modeling. International Journal of Rf and Microwave Computer-aided Engineering, 29(6), 2019.
[8] Y.; Wen C.L. Yong, J.H.; Ting. PADS software foundation and application examples. Publishing House of Electronics Industry, 2019.
[9] Teng Li. A study on si simulation of high-speed interconnection channel. Electronics and Packaging, 18(12):37–40, 2018.
[10] H. Sasaki, M. Kanazawa, T. Sudo, A. Tomishima, and T. Kaneko. New frequency dependent target impedance for ddr3 memory system. pages 1–4, 2011.
[11] C. Liao, B. Mutnury, C. Chen, and Y. Lee. Pcb stack-up design and optimization for next generation speeds. In 2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS), pages 155–158, 2016.
[12] Nastaran Soleimani, Mohammad GH Alijani, and Mohammad H Neshati. Crosstalk analysis at near-end and far-end of the coupled transmission lines based on eigenvector decomposition. AEU-International Journal of Electronics and Communications, 112:152944, 2019.
[13] X. Ye and C. Ye. Transmission lines and basic signal integrity. In 2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI PI), pages 1–51, 2018.
[14] Wang Xiaojing, Ye Ming, and Ma Yan. Research crosstalk between parallel interconnects. Electronic Measurement Technology, 2015.
[15] J. Fan, X. Ye, J. Kim, B. Archambeault, and A. Orlandi. Signal integrity design for high-speed digital circuits: Progress and directions. IEEE Transactions on Electromagnetic Compatibility, 52(2):392–400, 2010.
[16] Dong Zhang, L. I. Qiong, and Qianqin Qin. Application of simulation analysis based on ibis model to sdram pcb design. Journal of Wuhan University, 2011.
[17] A. K. Pandey. Power-aware signal integrity analysis of ddr4 data bus in onboard memory module. In 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), pages 1–4, 2016.
[18] Nastaran Soleimani, Mohammad GH Alijani, and Mohammad H Neshati. Crosstalk analysis of multi-microstrip coupled lines using transmission line modeling. International Journal of RF and Microwave Computer-Aided Engineering, 29(6):e21677, 2019.
[19] S. M¨uller, T. Reuschel, R. Rimolo-Donadio, Y. H. Kwark, H. Br¨uns, and C. Schuster. Energy-aware signal integrity analysis for high-speed pcb links. IEEE Transactions on Electromagnetic Compatibility, 57(5):1226– 1234, 2015.
[20] Jie Tang, Yi Gong, and Zhen Guo Yang. Failure analysis on cracking of blind and buried vias of printed circuit board for high-end mobile phones. Soldering and Surface Mount Technology, 31(4), 2019.
[21] Liu Lu, Cao Yuesheng, and Duo Ruihua. Design and realization of high-density fdr interconnection switch board. Computer Engineering, (6):3, 2016.
[22] M S Al Salameh and M M Ababneh. Selecting printed circuit board parameters using swarm intelligence to minimize crosstalk between adjacent tracks. International Journal of Numerical Modelling-electronic Networks Devices and Fields, 28(1):21–32, 2015.
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Authors and Affiliations

Kaixing Cheng
1
Zhongqiang Luo
1
Xingzhong Xiong
1
Xiaohan Wei
1

  1. Artificial Intelligence Key Laboratory of Sichuan Province, Sichuan University of Science and Engineering, Yibin, China
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Abstract

To overcome the detrimental influence of α impulse noise in power line communication and the trap of scarce prior information in traditional noise suppression schemes , a power iteration based fast independent component analysis (PowerICA) based noise suppression scheme is designed in this paper. Firstly, the pseudo-observation signal is constructed by weighted processing so that single-channel blind separation model is transformed into the multi-channel observed model. Then the proposed blind separation algorithm is used to separate noise and source signals. Finally, the effectiveness of the proposed algorithm is verified by experiment simulation. Experiment results show that the proposed algorithm has better separation effect, more stable separation and less implementation time than that of FastICA algorithm, which also improves the real-time performance of communication signal processing.

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Authors and Affiliations

Wei Zhang
ORCID: ORCID
Zhongqiang Luo
Xingzhong Xiong

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