Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 19
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

Is the category of “becoming” relative? This question accompanies the considerations undertaken in this article. It is the starting point for the reflection on the understanding of the designations of the expression “to become” in the metaphysical, epistemological and linguistic aspects. The results of this reflection are to serve adequate interpretations of the text. In the applicative part of the article both the fundamentals of text interpretation and the risks resulting from different cognitive perspectives are discussed. The source of these risks is seen primarily in misunderstanding the essence and the category of becoming.
Go to article

Authors and Affiliations

Grzegorz Pawłowski
1
ORCID: ORCID

  1. Uniwersytet Warszawski
Download PDF Download RIS Download Bibtex

Abstract

In this paper we show how formal computer science concepts—such as encoding, algorithm or computability—can be interpreted philosophically, including ontologically and epistemologically. Such interpretations lead to questions and problems, the working solutions of which constitute some form of pre-philosophical worldview. In this work we focus on questions inspired by the IT distinction between digitality and analogicity, which has its mathematical origin in the mathematical distinction between discreteness and continuity. These include the following questions: 1) Is the deep structure of physical reality digital or analog, 2) does the human mind resemble a more digital or analog computational system, 3) does the answer to the second question give us a cognitively fruitful insight into the cognitive limitations of the mind? As a particularly important basis for the above questions, we consider the fact that the computational power (i.e., the range of solvable problems) of some types of analog computations is greater than that of digital computations.

Go to article

Authors and Affiliations

Paweł Stacewicz
Download PDF Download RIS Download Bibtex

Abstract

This paper addresses the issue of the development of FOR DREAD THAT – a negative purpose subordinator in the history of the English language. The theoretical foundation of this work are the mechanisms of grammaticalisation suggested by Heine and Kuteva in many works of theirs. The gathered material shows that the development of this relatively rarely used subordinator constitutes a case of a typical grammaticalisation whose rise might have been the result of analogy with FOR FEAR THAT.

Go to article

Authors and Affiliations

Andrzej M. Łęcki
Download PDF Download RIS Download Bibtex

Abstract

Analog circuits need more effective fault diagnosis methods. In this study, the fault diagnosis method of analog circuits was studied. The fault feature vectors were extracted by a wavelet transform and then classified by a generalized regression neural network (GRNN). In order to improve the classification performance, a wolf pack algorithm (WPA) was used to optimize the GRNN, and a WPA-GRNN diagnosis algorithm was obtained. Then a simulation experiment was carried out taking a Sallen–Key bandpass filter as an example. It was found from the experimental results that the WPA could achieve the preset accuracy in the eighth iteration and had a good optimization effect. In the comparison between the GRNN, genetic algorithm (GA)-GRNN and WPA-GRNN, the WPA-GRNN had the highest diagnostic accuracy, and moreover it had high accuracy in diagnosing a single fault than multiple faults, short training time, smaller error, and an average accuracy rate of 91%. The experimental results prove the effectiveness of the WPA-GRNN in fault diagnosis of analog circuits, which can make some contributions to the further development of the fault diagnosis of analog circuits.

Go to article

Authors and Affiliations

Hui Wang
Download PDF Download RIS Download Bibtex

Abstract

This paper is focused on multiple soft fault diagnosis of linear time-invariant analog circuits and brings a method that achieves all objectives of the fault diagnosis: detection, location, and identification. The method is based on a diagnostic test arranged in the transient state, which requires one node accessible for excitation and two nodes accessible for measurement. The circuit is specified by two transmittances which express the Laplace transform of the output voltages in terms of the Laplace transform of the input voltage. Each of these relationships is used to create an overdetermined system of nonlinear algebraic equations with the circuit parameters as the unknown variables. An iterative method is developed to solve these equations. Some virtual solutions can be eliminated comparing the results obtained using both transmittances. Three examples are provided where laboratory or numerical experiments reveal effectiveness of the proposed method.
Go to article

Bibliography

[1] D. Gizopoulos, Advances in electronic testing. Challenges and methodologies. (Springer, Dordrecht, 2006)
[2] P. Kabisatpathy, A. Barua and S. Sinha, Fault diagnosis of analog integrated circuits. (Springer, Dordrecht, 2005).
[3] Y. Sun (ed.), Test and diagnosis of analog mixed-signal and RF integrated circuits: the system on chip approach, (IET Digital Library, UK, 2008)
[4] D. Binu, B.S. Kariyappa, “A survey on fault diagnosis of analog circuits: Taxonomy and state of the art”, Int. J. Electron. Commun. (AEÜ), vol. 73, pp. 68-83, 2017. doi: 10.1016/j.aeue.2017.01.002.
[5] Z. Czaja, “Using a square-wave signal for fault diagnosis of analog parts of mixed-signal electronic embedded systems”, IEEE Trans. Instrum. Meas., vol. 57, pp. 1589-1595, 2008. doi: 10.1109/TIM.2008.925342
[6] H. Han, H. Wang, S. Tian, N. Zhang, “A new analog circuit fault diagnosis method based on improved Mahalanobis distance”, J. Electron. Test., vol. 29, pp. 95–102, 2013. https://doi.org/10.1007/s10836-012- 5342-z.
[7] Ch. Yang, S. Tian, B. Long, F. Chen, “Methods of handling the tolerance and test-point selection problem for analog-circuit fault diagnosis”, IEEE Trans. Instrum. Means., vol. 60, pp. 176-185, 2011. doi: 10.1109/TIM.2010.2050356
[8] Q.Z. Zhou, Y.L. Xie, X.F. Li, D.J. Bi, X. Xie, S.S. Xie, “Methodology and equipments for analog circuit parametric faults diagnosis based on matrix eigenvalues”, IEEE Trans. Appl. Superconductivity, vol. 24, pp. 1–6, 2014. https://doi.org/10.1109/TASC.2014.2340447.
[9] Y. Deng, Y. N. Liu, “Soft fault diagnosis in analog circuits based on bispectral models”, J. Electron. Test., vol. 33, pp. 543-557, 2017. https://doi.org/10.1007/s10836-017-5686-5.
[10] S. Djordjevic, M.T. Pesic, “A fault verification method based on the substitution theorem and voltage-current phase relationship”, J. Electron. Test., vol. 36, pp. 617-629, 2020. https://doi.org/10.1007/s10836-020- 05901-5.
[11] T. Gao, J. Yang, S. Jiang, “A novel incipient fault diagnosis method for analog circuits based on GMKL-SVM and wavelet fusion feature”. IEEE Trans. Instrum. Meas., vol. 70, 2021. https://doi.org/10.1109/TIM.2020.3024337.
[12] Y. Li, R. Zhang, Y. Guo, P. Huan, M. Zhang, “Nonlinear soft fault diagnosis of analog circuits based on RCCA-SVM”, IEEE Access., vol. 8, pp. 60951-60963, 2020. doi.org/10.1109/ACCESS.2020.2982246.
[13] M. Tadeusiewicz, S. Hałgas, “A new approach to multiple soft fault diagnosis of analog BJT and CMOS circuits”, IEEE Trans. Instrum. Meas., vol. 64, pp. 2688–2695, 2015. https://doi.org/10.1109/TIM.2015.2421712.
[14] M. Tadeusiewicz, S. Hałgas, “A method for local parametric fault diagnosis of a broad class of analog integrated circuits”, IEEE Trans. Instrum. Meas., vol. 67, pp. 328–337, 2018. https://doi.org/10.1109/TIM.2017.2775438.
[15] Y. Xie, X. Li, S. Xie, X. Xie, Q. Zhou, “Soft fault diagnosis of analog circuits via frequency response function measurements”, J. Electron. Test., vol. 30, pp. 243–249, 2014. https://doi.org/10.1007/s10836-014- 5445-9.
[16] M. Tadeusiewicz, S. Hałgas, M. Korzybski, “An algorithm for soft-fault diagnosis of linear and nonlinear circuits”, IEEE Trans. Circ. Syst.-I., vol. 49, pp. 1648-1653, 2002. doi: 10.1109/TCSI.2002.804596.
[17] M. Tadeusiewicz, S. Hałgas, “Soft fault diagnosis of linear circuits with the special attention paid to the circuits containing current conveyors”, Int. J. Electron Commun. (AEÜ), vol. 115, 2020. https://doi.org/10.1016/j.aeue.2019.153036.
[18] M. Tadeusiewicz and S. Hałgas, “A method for multiple soft fault diagnosis of linear analog circuits”, Measurement, vol. 131, pp. 714-722, 2019. doi: 10.1016/j.measurement.2018.09.001.
[19] M. Jahangiri, F. Razaghian, “Fault detection in analogue circuit using hybrid evolutionary algorithm and neural network”, Analog Int. Cir. Sig. Proc., vol. 80, pp. 551-556, 2014. https://doi.org/10.1007/s10470-014- 0352-7
[20] P. Jantos, D. Grzechca, J. Rutkowski, “Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits”, Bull. Polish Acad. Scien., vol. 60, pp. 133-142, 2012. doi: 10.2478/v10175- 012-0019-4
[21] C. Yang, “Multiple soft fault diagnosis of analog filter circuit based on genetic algorithm”, IEEE Access., vol. 8, pp. 8193-8201, 2020. https://doi.org/10.1109/ACCESS.2020.2964054.
[22] D. Grzechca, “Soft fault clustering in analog electronic circuits with the use of self organizing neural network”, Metrol Meas Syst., vol. 8, pp. 555–568, 2011. doi: 10.2478/v10178-011-0054-8
[23] B. Long, M. Li, H. Wang, S. Tian, “Diagnostics of analog circuits based on LS-SVM using time-domain features”, Circuits Syst. Signal. Process., vol. 32, pp. 2683-2706, 2013. https://doi.org/10.1007/s00034-013-9614-3
[24] R. Sałat, S, Osowski, “Support Vector Machine for soft fault location in electrical circuits”, J. Intelligent Fuzzy Systems., vol. 22, pp. 21-31, 2011. doi: 10.3233/IFS-2010-0471.
[25] D. Grzechca, “Construction of an expert system based on fuzzy logic for diagnosis of analog electronic circuits”, Int. Journal of Electronic and Telecomunications, vol. 61, pp. 77-82, 2015. doi: 10.1515/eletel-2015- 0010
[26] P. Bilski, “Analysis of the ensemble of regression algorithms for the analog circuit parametric identification”, Measurement, vol. 170, pp. 503–514, 2020. https://doi.org/10.1016/j.measurement.2020.107829.
[27] M. Tadeusiewicz, M. Ossowski, “A verification technique for multiple soft fault diagnosis of linear analog circuits”, Int. Journal of Electronic and Telecomunications, vol. 64, pp. 83-89, 2018. doi: 10.24425/118150.
[28] M. Tadeusiewicz, M. Ossowski, “Modeling analysis and diagnosis of analog circuits in z-domain”, J. Circ. Syst. Comput, vol. 29, no. 02, 2020. https://doi.org/10.1142/S0218126620500280
[29] G. Fedi, S. Manetti, M.C. Piccirilli, J. Starzyk, “Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits”, IEEE Trans. Circ. Syst.-I, vol. 46, pp. 779-787, 1999. doi: 10.1109/81.774222
[30] S. Manetti, M.C. Piccirilli, “A singular-value decomposition approach for ambiguity group determination in analog circuits”, IEEE Trans. Circ. Syst.-I, vol. 50 pp. 477-487, 2003. doi: 10.1109/TCSI.2003.809811.
[31] S. Saeedi, S.H. Pishgar, M. Eslami, “Optimum test point selection method for analog fault dictionary techniques”, Analog Integr. Circuits Signal Processing., vol. 100, pp. 167-179, 2019. https://doi.org/10.1007/s10470-019-01453-7.
[32] X. Tang, A. Xu, R. Li, M. Zhu, J. Dai, “Simulation-based diagnostic model for automatic testability analysis of analog circuit”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., vol. 37, pp. 1483-1493, 2018. https://doi.org/10.1109/TCAD.2017.2762647.
Go to article

Authors and Affiliations

Michał Tadeusiewicz
1
Marek Ossowski
1
Marek Korzybski
1

  1. Lodz University of Technology, Department of Electrical, Electronic, Computer and Control Engineering, Lodz, Poland
Download PDF Download RIS Download Bibtex

Abstract

This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog- AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
Go to article

Bibliography

[1] N. Arora, “MOSFET Modeling for VLSl Circuit Simulation: Theory and Practice,” World Scientific, 1993.
[2] International Technology Roadmap for Semiconductors. Available: http://www.itrs2.net, 2017.
[3] O. Samy, H. Abdelhamid, Y. Ismail, A. Zekry, “A 2D compact model for lightly doped DGMOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs),” Microelectronics reliability, 2016, 67, 82-88.
[4] J-P. Colinge, “FinFETs and Other Multi-Gate Transistors,” Springer, 2008.
[5] A. Amara, “Planar Double-Gate Transistor, From Technology to Circuit,” Springer, 2009.
[6] D. Stefanović, M. Kayal, M, “Structured Analog CMOS Design,” Springer, 2008.
[7] A. Mangla, M.-A. Chalkiadaki, F. Fadhuile, T. Taris, Y. Deval, C. C. Enz, “Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model,” Microelectronics journal, 2013, 44, 570-575.
[8] A.B. Bhattacharyya, “Compact MOSFET models for VLSI design,” Wiley, 2009.
[9] B. Smaani, S. Latreche, B. Iñiguez, „Compact drain-current model for undoped cylindrical surrounding-gate MOSFETs including short channel effects,” J. Appl. Phys., 2013, 114.
[10] J-M. Sallese, F. Krummenacher, F. Prégaldiny, „A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism,” Solid-State Electronics, 2012, 49, 485-489.
[11] O. Moldovan, F. Lime, S. Barraud, B. Smaani, „Experimentally verified drain-current model for variable barrier transistor,” IET Electronics Letters, 2015, 51, 17, 364–366.
[12] J. Alvarado, B. Iñiguez, M. Estrada, “Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation,” Int. J. Numer. Model, 2010, 23, 88–106.
[13] O. Cobianu, M. Soffke, A. Glesner, “Verilog-A model of an undoped symmetric dual-gate MOSFET,” Int. Adv. Radio Sci, 2006, 4, 303–306.
[14] M. Cheralathan, E. Contreras, J. Alvarado, “Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models,” Microelectronics Journal, 2013, 44, 80–85. [15] Verilog-AMS User Manual, Accellera 2006.
[16] B. Smaani, M. Bella, S. Latreche, “Compact Modeling of Lightly Doped Nanoscale DG MOSFET Transistor,” Applied Mechanics and Materials, 2014, 492, 06–10.
[17] O. Samy, H. Abdelhamid , Y. Ismail, A. Zekry, “A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs),” Microelectronics Reliability, 2016, 67, 82-88.
[18] Y. Taur, X. Liang, “A continuous, analytic drain-current model for DG MOSFETs,” IEEE Electron device Letters, 2004, 25, 2, 107–109.
[19] J-M. Sallese, A. S. Porret, “A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation,” Solid-State Electronics, 2000, 44, 887-894.
[20] H. Børli, S. Kolberg, “Capacitance modeling of short-channel double-gate MOSFETs,” Solid-State Electronics, 2008, 52, 1486–1490.
[21] C. Enz, F. Krummenacher, A.Vittoz, “An analytical MOS Transistor Model Valid in All Regions of Operation Dedicated to low voltage and low current applications,” Analog and integrated Circuits and Signal Processing, 1995, 8, 83-114.
[22] M. Bella, S. Latreche, C. Gontrand, “Nanoscale DGMOSFET: DC modification and Analysis of Noise in RF Oscillator,” Journal of Applied Sciences,2015, 5, 800–807.
[23] R. Blaise, W. Tekam, J. Kengne, G. D. Kenmoe, “High frequency Colpitts’ oscillator: A simple configuration for chaos generation,” Chaos, Solitons & Fractals, 2019, 126, 351–360.
[24] A.Rana1, P. Gaikwad, “Colpitts oscillator: design and performance optimization,” Int. Journal of Applied Sciences and Engineering Research, 2014, 3, 913–919.
[25] SMASH User Manual Version 5.18 Release, 2012.
[26] Device simulator ATLAS, Silvaco International, 2007.
Go to article

Authors and Affiliations

Billel Smaani
1
Yacin Meraihi
2
Fares Nafa
2
Mohamed Salah Benlatreche
3
Hamza Akroum
4
Saida Latreche
5

  1. Ingénierie des Systémes Electriques Department, Faculty of Technology, Boumerdes University, Algeria
  2. Laboratoire d'Ingénierie et Systèmes de Télécommunications, Faculté de Technologie, Boumerdes, Algeria
  3. Centre Universitaire Abdel Hafid Boussouf Mila, Algeria
  4. Laboratoire d’Automatique Appliquée, Université M’Hamed Bougara de Boumerdes, Algeria
  5. Laboratoire Hyperfréquences et Semiconducteurs, Electronique Department, Constantine 1 University, Algeria
Download PDF Download RIS Download Bibtex

Abstract

Abstract. The paper introduces a neuromorphic computational approach for breathing rate monitoring of a single person observed using a Frequency-Modulated Continuous Wave radar. The architecture, aimed at implementation in analog hardware to ensure high energy efficiency and to provide system operation longevity, comprises two main functional modules. The first one is a data preprocessing unit aimed at the extraction of information relevant to the analysis objective, whereas the second one is a pre-trained recurrent neural regressor, which analyzes sequences of incoming samples and estimates the breathing rate. To ensure compatibility with neural processing and to achieve simplicity of underlying resources, several solutions were proposed for the data preprocessing module, which provides range-wise space segmentation, selection of a bin of interest (comprising the dominant motion activity), and delivery of data to regressor inputs. To implement these functions, we introduce an appropriate chirp frequency modulation scheme, apply a neuromorphic filtering procedure and use a Winner-Takes-All network for extracting information from the bin of interest. The architecture has been experimentally verified using a dataset of indoor recordings supplied with reference data from a Zephyr BioHarness device. We show that the proposed architecture is capable of making correct breathing rate estimates while being feasible for analog implementation. The mean squared regression error with respect to the Zephyr-produced reference values is approximately 3.3 breaths per minute (with a deviation of ±0:27 in the 95% confidence interval) and the estimates are produced by a recurrent, GRU-based neural regressor, with a total of only 147 parameters.
Go to article

Authors and Affiliations

Krzysztof Ślot
1
ORCID: ORCID
Piotr Łuczak
1
ORCID: ORCID
Sławomir Hausman
2
ORCID: ORCID

  1. Institute of Applied Computer Science, Lodz University of Technology
  2. Institute of Electronics, Lodz University of Technology
Download PDF Download RIS Download Bibtex

Abstract

The method described in this work allows to determine the optimal distribution of pulses of digital signal as well as the non-linear mathematical model based on a multiple regression statistical analysis, which are specialized to an effective and low-cost testing of functional parameters in analog electronic circuits. The aim of this concept is to simplify the process of analog circuit specification validation and minimize hardware implementation, time and memory requirements during the testing stage. This strategy requires simulations of the analyzed analog electronic circuit; however, this effort is done only once – before the testing stage. Then, validation of circuit specification can be obtained after a quick, very low-cost procedure without time consuming computations and without expensive external measuring equipment usage. The analyzed test signature is a time response of the analog circuit to the stream of digital pulses for which distributions were determined during evolutionary optimization cycles. Besides, evolutionary computations assure determination of the optimal form and size of the non-linear mathematical formula used to estimate specific functional parameters. Generally, the obtained mathematical model has a structure similar to the polynomial one with terms calculated by means of multiple regression procedure. However, a higher ordered polynomial usage makes it possible to reach non-linear estimation model that improves accuracy of circuit parametric identification. It should be noted that all the evolutionary calculations are made only at the before test stage and the main computational effort, for the analog circuit specification test design, is necessary only once. Such diagnosing system is fully synchronized by a global digital signal clock that precisely determines time points of the slopes of input excitation pulses as well as acquired output signature samples. Efficiency of the proposed technique is confirmed by results obtained for examples based on analog circuits used in previous (and other) publications as test benchmarks.

Go to article

Authors and Affiliations

T. Golonek
Ł. Chruszczyk
Download PDF Download RIS Download Bibtex

Abstract

Analogy and language contact represent endogenous and exogenous factors of language change. Although both processes have been discussed in the realm of Arabic dialectology, they are usually treated as two unrelated scenarios. The central question that this study posits is whether those are two functionally independent phenomena, or they can operate synergetically. The primary focus of this paper is two typologically distinct Jewish dialects, i.e. sedentary Gabes (Southern Tunisia), and exhibiting numerous Bedouin features Wad-Souf (Eastern Algeria). Based on new data obtained from fieldwork, this paper accounts for five cases of grammar evolution within verb morphology and syntax through the lens of analogy and language contact. It raises the possibility that under certain circumstances, language change can occur at the intersection of endogenous and exogenous factors.
Go to article

Authors and Affiliations

Wiktor Gębski
1
ORCID: ORCID

  1. University of Cambridge, United Kingdom
Download PDF Download RIS Download Bibtex

Abstract

The article is an attempt to look at the mediaevalist work of Jacek Banaszkiewicz through the prism of statements of other scholars using the comparative method (including M. Handelsman, M. Małowist, M. Tymowski, K. Modzelewski). The aim is to answer the question of whether there is a set of guidelines that every comparatist should follow. The specific issues discussed here include the role of difference and similarity in comparison, the notions of function, analogy and homology, geographical and chronological limitations of comparative studies, and the role of influence and reception.
Go to article

Authors and Affiliations

Rafał Rutkowski
1
ORCID: ORCID

  1. Instytut Archeologii i Etnologii PAN
Download PDF Download RIS Download Bibtex

Abstract

The present work involved an extensive outdoor performance testing program of a solar water heating system that consists of four evacuated tube solar collectors incorporating four wickless heat pipes integrated to a storage tank. Tests were conducted under the weather conditions of Baghdad, Iraq. The heat pipes were of 22 mm diameter, 1800 mm evaporator length and 200 mm condenser length. Three heat pipe working fluids were employed, ethanol, methanol, and acetone at an inventory of 50% by volume of the heat pipe evaporator sections. The system was tested outdoors with various load conditions. Results showed that the system performance was not sensitive to the type of heat pipe working fluid employed here. Improved overall efficiency of the solar system was obtained with hot water withdrawal (load conditions) by 14%. A theoretical analysis was formulated for the solar system performance using an energy balance based iterative electrical analogy formulation to compare the experimental temperature behavior and energy output with theoretical predictions. Good agreement of 8% was obtained between theoretical and experimental values.

Go to article

Authors and Affiliations

Hassan Naji Salman Al-Joboory
Download PDF Download RIS Download Bibtex

Abstract

This paper presents exemplary exercise on the fundamentals of signal processing course which is offered for second year bachelor level students. Application of Field Programmable Analog Array (FPAA) for pulse amplitude modulation (PAM) exercise is described with signal processing laboratory. There are presented two methods for implementing PAM modulation and demodulation technique in FPAA module. Example configuration files are available form Authors’ web site.

Go to article

Authors and Affiliations

Damian Grzechca
Lukas Chruszczyk
Download PDF Download RIS Download Bibtex

Abstract

This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. Development of mathematical models of errors, quantitative assessment of these errors taking into account modern components and assessing the accuracy of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback were presented. (Logarithmic ADC with accumulation of charge and impulse feedback – analysis and modeling).
Go to article

Bibliography

[1] S. Purighalla, B. Maundy, “84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18-μm Technology,” IEEE Transactions on Circuits and Systems II: Express Briefs, 58 (2011), no.5, pp. 279-283
[2] J. Lee, J. Kang, S. Park, J. Seo, J. Anders, J. Guilherme, M. P. Flynn, “A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC,” IEEE Journal Of Solid-State Circuits, 44 (2009), no.10, pp. 2755-2765
[3] B. Maundy, D. Westwick, S. Gift, “On a class of pseudo-logarithmic amplifiers suitable for use with digitally switched resistors,” Int. J. of Circuit Theory and Applications, vol. 36 (2008), no.1, pp. 81–108
[4] B. Maundy, D. Westwick, S. Gift, (2007) “A useful pseudo-logarithmic circuit,” Microelectronics International, Vol. 24 Iss: 2, pp.35 - 45
[5] M. Alirieza, L. Jing and J. Dileepan, “Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture,” Sensors, 13(8), pp. 10765-10782, August 2013
[6] J. Guilherme, J. Vital, Jose Franca, “A True Logarithmic Analog-to-Digital Pipeline Convener with 1.5bitistage and Digital Correction,” Proc. IEEE International Conference on Electronics Circuits and Systems, pp. 393-396, Malta 2001
[7] G. Bucci, M. Faccio, C. Landi, “The performance test of a piece-linear A/D converter,” IEEE Instrumentation and Measurement Technology Conference, St. Paul USA May 1998, pp.1223.1228
[8] J. Guilherme, J. Vital, J. Franca, “A CMOS Logarithmic Pipeline A/D Converter with a Dynamic Range of 80 dB,” IEEE Electronics, Circuits and Systems, 2002. 9th International Conference on, (2002), no.3/02, pp. 193-196
[9] J. Sit and R. Sarpeshkar, “A Micropower Logarithmic A/D With Offset and Temperature Compensation,” IEEE J. Solid-State Circuits, 39 (2004), nr. 2, pp. 308-319
[10] J. Mahattanakul, “Logarithmic data converter suitable for hearing aid applications,” Electronic Letters, 41 (2005), no.7, pp. 31-32
[11] S. Sirimasakul, A. Thanachayanont, W. Jeamsaksiri, “Low-Power Current-Mode Logarithmic Pipeline Analog-to-Digital Converter for ISFET based pH Sensor,” IEEE ISCIT, 2009, no.6/09, pp. 1340-1343
[12] M. Santosa, N. Hortaa, J. Guilherme, “A survey on nonlinear analog-to-digital converters,” Integration, the VLSI Journal, Volume 47, Issue 1, pp. 12–22, January 2014
[13] Z.R. Mychuda, “Logarithmic Analog-To-Digital Converters – ADC of the Future,” Prostir, Lviv, Ukraine 2002, pp. 242
[14] A. Szcześniak, Z Myczuda, “A method of charge accumulation in the logarithmic analog-to-digital converter with a successive approximation,” Electrical Review, 86 (2010), no.10, pp. 336-340
[15] A. Szcześniak, U. Antoniw, Ł. Myczuda, Z. Myczuda, „Logarytmiczne przetworniki analogowo-cyfrowe z nagromadzeniem ładunku i impulsowym sprzężeniem zwrotnym,” Electrical Review, R. 89 no. 8/2013, pp. 277 – 281
[16] A. Szcześniak, Z. Myczuda, „Analiza prądów upływu logarytmicznego przetwornika analogowo-cyfrowego z sukcesywną aproksymacją,” Electrical Review, 88 (2012), no. 5а, pp. 247-250
[17] J.H. Moon, D. Y. Kim, M. K. Song, Patent No. KR20110064514A, “Logarithmic Single-Slope Analog Digital Convertor, Image Sensor Device And Thermometer Using The Same, And Method For Logarithmic Single-Slope Analog Digital Converting,”
[18] J. Gorisse, F. A. Cathelin, A. Kaiser, E. Kerherve Patent No. EP2360838A1, “Method for logarithmic analog-to-digital conversion of an analog input signal and corresponding apparatus,”
[19] R. Offen Patent No. DE102008007207A1 “Logarithmierender Analog-Digital Wandler,”
[20] H. Suzunaga Patent No. US20080054163A1, “Logarithmic-compression analog-digital conversion circuit and semiconductor photosensor device,”
Go to article

Authors and Affiliations

Zynoviy Mychuda
1
Lesya Mychuda
1
Uliana Antoniv
1
Adam Szcześniak
2

  1. Lviv Polytechnic National University, Department of the Computer-Assisted Systems of Automation, Ukraine
  2. University of Technology in Kielce, Department of Mechatronics and Machine Building, Poland
Download PDF Download RIS Download Bibtex

Abstract

This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. LADC construction, principle of operation and dynamic properties were presented. They can also be part of more complex converters and systems based on LADC. LADC of this class is perspective for implementation in the form of integrated circuit, as the number of switched capacitors needed to conversion is minimized to one capacitor. (Logarithmic ADC with accumulation of charge and impulse feedback – construction, principle of operation and dynamic properties)
Go to article

Bibliography

[1] S. Purighalla, B. Maundy, “84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18-μm Technology”, IEEE Transactions on Circuits and Systems II: Express Briefs, 58 (2011), no.5, pp. 279-283
[2] J. Lee, J. Kang, S. Park, J. Seo, J. Anders, J. Guilherme, M. P. Flynn, “A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC,” IEEE Journal Of Solid-State Circuits, 44 (2009), no.10, pp. 2755-2765
[3] B. Maundy, D. Westwick, S. Gift, “On a class of pseudo-logarithmic amplifiers suitable for use with digitally switched resistors,” Int. J. of Circuit Theory and Applications, vol. 36 (2008), no.1, pp. 81–108
[4] B. Maundy, D. Westwick, S. Gift, (2007) “A useful pseudo-logarithmic circuit,” Microelectronics International, Vol. 24 Iss: 2, pp.35 - 45
[5] M. Alirieza, L. Jing and J. Dileepan, “Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture,” Sensors, 13(8), pp. 10765- 10782, August 2013
[6] J. Guilherme, J. Vital, Jose Franca, “A True Logarithmic Analog-to- Digital Pipeline Convener with 1.5bitistage and Digital Correction,” Proc. IEEE International Conference on Electronics Circuits and Systems, pp. 393-396, Malta 2001
[7] G. Bucci, M. Faccio, C. Landi, “The performance test of a piece-linear A/D converter,” IEEE Instrumentation and Measurement Technology Conference, St. Paul USA May 1998, pp.1223.1228
[8] J. Guilherme, J. Vital, J. Franca, “A CMOS Logarithmic Pipeline A/D Converter with a Dynamic Range of 80 dB,” IEEE Electronics, Circuits and Systems, 2002. 9th International Conference on, (2002), no.3/02, pp. 193-196
[9] J. Sit and R. Sarpeshkar, “A Micropower Logarithmic A/D With Offset and Temperature Compensation,” IEEE J. Solid-State Circuits, 39 (2004), nr. 2, pp. 308-319
[10] J. Mahattanakul, “Logarithmic data converter suitable for hearing aid applications,” Electronic Letters, 41 (2005), no.7, pp. 31-32
[11] S. Sirimasakul, A. Thanachayanont, W. Jeamsaksiri, “Low-Power Current-Mode Logarithmic Pipeline Analog-to-Digital Converter for ISFET based pH Sensor,” IEEE ISCIT, 2009, no.6/09, pp. 1340-1343
[12] M. Santosa, N. Hortaa, J. Guilherme, “A survey on nonlinear analog-todigital converters,” Integration, the VLSI Journal, Volume 47, Issue 1, pp. 12–22, January 2014
[13] Z.R. Mychuda, “Logarithmic Analog-To-Digital Converters – ADC of the Future,” Prostir, Lviv, Ukraine 2002, pp. 242
[14] A. Szcześniak, Z Myczuda, “A method of charge accumulation in the logarithmic analog-to-digital converter with a successive approximation,” Electrical Review, 86 (2010), no.10, pp. 336-340
[15] A. Szcześniak, U. Antoniw, Ł. Myczuda, Z. Myczuda, „Logarytmiczne przetworniki analogowo-cyfrowe z nagromadzeniem ładunku i impulsowym sprzężeniem zwrotnym,” Electrical Review, R. 89 no. 8/2013, pp. 277 – 281
[16] A. Szcześniak, Z. Myczuda, „Analiza prądów upływu logarytmicznego przetwornika analogowo-cyfrowego z sukcesywną aproksymacją,” Electrical Review, 88 (2012), no. 5а, pp. 247-250
[17] J.H. Moon, D. Y. Kim, M. K. Song, Patent No. KR20110064514A, “Logarithmic Single-Slope Analog Digital Convertor, Image Sensor Device And Thermometer Using The Same, And Method For Logarithmic Single-Slope Analog Digital Converting,”
[18] J. Gorisse, F. A. Cathelin, A. Kaiser, E. Kerherve Patent No. EP2360838A1, “Method for logarithmic analog-to-digital conversion of an analog input signal and corresponding apparatus,”
[19] R. Offen Patent No. DE102008007207A1 “Logarithmierender Analog- Digital Wandler,”
[20] H. Suzunaga Patent No. US20080054163A1, “Logarithmic-compression analog-digital conversion circuit and semiconductor photosensor device,”
Go to article

Authors and Affiliations

Zynoviy Mychuda
1
Lesya Mychuda
1
Uliana Antoniv
1
Adam Szcześniak
2

  1. Lviv Polytechnic National University, Department of the Computer-Assisted Systems of Automation, Ukraine
  2. University of Technology in Kielce, Department of Mechatronics and Machine Building, Poland
Download PDF Download RIS Download Bibtex

Abstract

The Jewish dialect of ʿĀna exhibits three synchronic vowel qualities for the prefix vowel in the prefix-conjugation of the first stem: a, ǝ, and u. While the latter vowel is an allophone of ǝ, the former two are independent phonemes. The existence of two phonemic prefix vowels, especially the vowel a, is intriguing in regional context since the reconstructed prefix vowel in qǝltu dialects is assumed to be *i. Therefore, this paper aims to outline the historical developments that led to this synchronic reality. It will argue that the prefix vowel a was borrowed from surrounding Bedouin dialects. As for the vowel ǝ, two hypotheses will be suggested to explain its existence: it either developed from the prefix vowel a in analogy to other cases of vowel raising, or it is simply a reflection of the older qǝltu prefix vowel. Regardless of which hypothesis we choose to follow, the assumed historical development has clearly not been finalised, resulting in synchronic free variation.
Go to article

Authors and Affiliations

Assaf Bar-Moshe
1
ORCID: ORCID

  1. Free University of Berlin, Germany
Download PDF Download RIS Download Bibtex

Abstract

The purpose of drumlin formation is to facilitate glacier flow. Drumlins form in a deforming layer between ice and ground, they produce a pimpled ground surface which causes less drag in the flowing system, after the fashion of the Prandtl effect which reduces boundary layer detachment (as in the flying golf ball). This pimpled surface has selforganising properties and this causes the development of a low drag situation. The drumlin field is the critical phenomenon; the formation of individual drumlins is a small part of the overall effect.
Go to article

Authors and Affiliations

Ian J. Smalley
Ping Lu
Ian F. Jefferson
Download PDF Download RIS Download Bibtex

Abstract

A hybrid artificial boundary condition (HABC) that combines the volume-based acoustic damping layer (ADL) and the local face-based characteristic boundary condition (CBC) is presented to enhance the absorption of acoustic waves near the computational boundaries. This method is applied to the prediction of aerodynamic noise from a circular cylinder immersed in uniform compressible viscous flow. Different ADLs are designed to assess their effectiveness whereby the effect of the mesh-stretch direction on wave absorption in the ADL is analysed. Large eddy simulation (LES) and FW-H acoustic analogy method are implemented to predict the far-field noise, and the sensitivities of each approach to the HABC are compared. In the LES computed propagation field of the fluctuation pressure and the frequency-domain results, the spurious reflections at edges are found to be significantly eliminated by the HABC through the effective dissipation of incident waves along the wave-front direction in the ADL. Thereby, the LES results are found to be in a good agreement with the acoustic pressure predicted using FW-H method, which is observed to be just affected slightly by reflected waves.

Go to article

Authors and Affiliations

Ruixian Ma
Zhansheng Liu
Con J. Dooloan
Danielle J. Moreau
Michał Czarnecki
Download PDF Download RIS Download Bibtex

Abstract

The authors update the issue disassembly-free control and correction of all components of the error of measuring channels with multi-bit analog-to-digital converters (ADCs). The main disadvantages of existing methods for automatic control of the parameters of multi-bit ADCs, in particular their nonlinearity, are identified. Methods for minimizing instrumental errors and errors caused by limited internal resistances of closed switches, input and output resistances of active elements are investigated. The structures of devices for determining the multiplicative and nonlinear components of the error of multi-bit ADCs based on resistive dividers built on single-nominal resistors are proposed and analyzed. The authors propose a method for the correction of additive, multiplicative and nonlinear components of the error at each of the specified points of the conversion range during non-disassembly control of the ADC with both types of inputs. The possibility of non-disassembly control, as well as correction of multiplicative and nonlinear components of the error of multi-bit ADCs in the entire range of conversion during their on-site control is proven. ADC error correction procedures are proposed. These procedures are practically invariant to the non-informative parameters of active structures with resistive dividers composed of single-nominal resistors. In the article the prospects of practical implementation of the method of error correction during non-dismantling control of ADC parameters using the possibilities provided by modern microelectronic components are shown. The ways to minimize errors are proposed and the requirements to the choice of element parameters for the implementation of the proposed technical solutions are given. It is proved that the proposed structure can be used for non-disassembly control of multiplicative and nonlinear components of the error of precision instrumentation amplifiers.
Go to article

Authors and Affiliations

Tetiana Bubela
1
Roman Kochan
2 3
Łukasz Więcław
2
Vasyl Yatsuk
1
Viktor Kuts
1
Jurij Yatsuk
4

  1. Lviv Polytecnic National University, Department of Information and Measurement Technologies, S. Bandery 12, 79013 Lviv, Ukraine
  2. University of Bielsko-Biala, Department of Informatics and Automation, Willowa 2, 43-309 Bielsko-Biała, Poland
  3. Lviv Polytecnic National University, Department of Specialized Computer Systems, S. Bandery 12, 79013 Lviv, Ukraine
  4. Lviv Polytecnic National University, Department of Computerized Automation Systems, S. Bandery 12, 79013 Lviv, Ukraine
Download PDF Download RIS Download Bibtex

Abstract

A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 megasamples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Go to article

Bibliography

[1] Y. Zhou, B. Xu and Y. Chiu, “A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC,” IEEE Journal of Solid-State Circuits 54, 8, 2207-2218, (2019). https://doi.org/10.1109/JSSC.2019.2915583.
[2] D. Oh, J. Kim, D. Jo, W. Kim, D. Chang and S. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” IEEE Journal of Solid-State Circuits 54, 1, 288- 297,(2019). https://doi.org/10.1109/JSSC.2018.2870554.
[3] A. Wu, J. Wu, and J. Huang, “Energy-efficient switching scheme for ultra-low voltage SAR ADC.”, Analog Integr Circ Sig Process 90, 507–511, (2017). https://doi.org/10.1007/s10470-016-0892-0
[4] M. Guo, J. Mao, S. Sin, H. Wei and R. P. Martins, “A 1.6- GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration,”IEEE Journal of Solid-State Circuits 55, 3,693-705, (2020). https://doi.org/10.1109/JSSC.2019.2945298.
[5] M. Davidovic, G. Zach, H. Zimmermann, “An 11-bit successive approximation analog-to-digital converter based on a combined capacitor-resistor network.”, Elektrotech. Inftech. 127, 98–102, (2010). https://doi.org/10.1007/s00502-010-0704-7
[6] D. Chang, W. Kim, M. Seo, H. Hong, and S. Ryu, “Normalized- Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC.”, IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 2, 322-332 (2017). https://doi.org/10.1109/TCSI.2016.2612692
[7] M. Shim et al.,“Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC”, IEEE Journal of Solid-State Circuits 52, 4, 1077-1090, (2017). https://doi.org/10.1109/JSSC.2016.2631299
[8] D. Zhang and A. Alvandpour, “A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs 63, 3, 244-248, (2016). https://doi.org/10.1109/TCSII.2015.2482618.
[9] S.A. Zahrai, M. Onabajo, “ Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power- Efficient Hybrid Data Converters.”, J. Low Power Electron. Appl. 8, 12, (2018). https://doi.org/10.3390/jlpea8020012
[10] S.Taheri, J. Lin, J. S. Yuan,“Security Interrogation and Defense for SAR Analog to Digital Converter.”, Electronics 6, 48, (2017). https://doi.org/10.3390/electronics6020048
[11] J. Kim, B. Sung, W. Kim and S. Ryu, “A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS”, IEEE Journal of Solid-State Circuits 48, 6, 1429-1441, (2013). https://doi.org/10.1109/JSSC.2013.2252516
[12] S. Danesh, J. Hurwitz, K. Findlater, D. Renshaw and R. Henderson, “A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design”, IEEE Journal of Solid-State Circuits 48, 3, 733-748, (2013). https://doi.org/10.1109/JSSC.2013.2237672
[13] L. Wang, M. LaCroix and A. C. Carusone, “A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.”, IEEE Transactions on Circuits and Systems II: Express Briefs 64, 12, 1367-1371, (2017). https://doi.org/10.1109/TCSII.2017.2726063
[14] F. M´arquez, et al., “A novel autozeroing technique for flash Analog-to-Digital converters.”, Integration 47, 1, 23-29, (2014). https://doi.org/10.1016/j.vlsi.2013.06.002
[15] Masumeh Damghanian, Seyed Javad Azhari, “A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications.”, Integration 57, 158-168, (2017). https://doi.org/10.1016/j.vlsi.2017.01.006
[16] Y. Wang, M. Yao, B. Guo, Z. Wu, W. Fan and J. J. Liou, “A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage,” IEEE Access 7, 93396- 93403,(2019). https://doi.org/10.1109/ACCESS.2019.2927514.
[17] A. Khatak, M. Kumar, S. Dhull, “An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits.”, J. Low Power Electron. Appl. 8, 33, (2018). https://doi.org/10.3390/jlpea8040033.
[18] B. Hershberg et al., “3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA 68-70, (2019). https://doi.org/10.1109/ISSCC.2019.8662319.
[19] U. Chio et al., “Design and Experimental Verification of a Power Effective Flash-SAR Sub ranging ADC.”, IEEE Transactions on Circuits and Systems II: Express Briefs 57, 8, 607-611, (2010). https://doi.org/10.1109/TCSII.2010.2050937
[20] Young-Deuk Jeon et al., “A dual-channel pipelined ADC with sub-ADC based on flash-SAR architecture.”, Circuits and Systems II: Express Briefs 59, 741-745. (2012). https://doi.org/10.1109/TCSII.2012.2222837
[21] Y. Lin et al.,“ A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.”, IEEE Transactions on Circuits and Systems I: Regular Papers 60, 3, 570-581, (2013). https://doi.org/10.1109/TCSI.2012.2215756
[22] J.I. Lee, J. Song, “Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count.”, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) 1-4, (2013). https://doi.org/10.1109/TENCON.2013.6718487
[23] A. Esmailiyan, F. Schembari and R. B. Staszewski, “A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump- Based Comparators in 28-nm CMOS,”IEEE Transactions on Circuits and Systems I: Regular Papers 67, 6, 1789-1802, (2020). https://doi.org/10.1109/TCSI.2020.2969804.
[24] J. Xu, et al., “Low-leakage analog switches for low-speed sample-and-hold circuits”, Microelectronics Journal 76, 22–27, (2018). https://doi.org/10.1016/j.mejo.2018.04.008
[25] M. Nazari, L. Sharifi,A. Aghajani, and O. Hashemipour, “A 12-bit high performance current-steering DAC using a new binary to thermometer decoder.”, 2016 24 Iranian Conference on Electrical Engineering (ICEE), Shiraz 2016 1919-1924, (2016). https://doi.org/10.1109/IranianCEE.2016.7585835
[26] H.S. Bindra et al., “A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.”, IEEE Journal of Solid-State Circuits 53, 7, 1902-1912, (2018). https://doi.org/10.1109/JSSC.2018.2820147
[27] A. Taghizadeh, Z.D. Koozehkanani, J. Sobhi, “A new high-speed lowpower and low-offset dynamic comparator with a current-mode offset compensation technique.”, AEU - Int. J. Electron. Commun. 81, 163–170, (2018). https://doi.org/10.1016/j.aeue.2017.07.018.
[28] M. Saberi and R. Lotfi,“ Segmented Architecture for Successive Approximation Analog-to-Digital Converters.”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 3, 593-606, (2014). https://doi.org/10.1109/TVLSI.2013.2246592
[29] Y. Haga et al., “Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique.”, 2005 IEEE International Symposium on Circuits and Systems 1, 220-223, (2005). https://doi.org/10.1109/ISCAS.2005.1464564.
[30] J. Lagos, B. P. Hershberg, E. Martens, P. Wambacq and J. Craninckx, “A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone- Degenerated Ring Amplifiers,” IEEE Journal of Solid-State Circuits 54, 3, 646-658, (2019). https://doi.org/10.1109/JSSC.2018.2889680.
[31] Y. Lim and M. P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC,” IEEE Journal of Solid-State Circuits 50, 12, 2901-2911, (2015). https://doi.org/10.1109/JSSC.2015.2463094
[32] B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.”, IEEE Communications Magazine 54, 4, 78-83, (2016). https://doi.org/10.1109/MCOM.2016.7452270
[33] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur196-199, (2010). https://doi.org/10.1109/APCCAS.2010.5774747.
[34] M. Hotta et al., “SAR ADC Architecture with Digital Error Correction.”. IEEJ Trans Elec Electron Eng 5, 651-659, (2010). https://doi.org/10.1002/tee.20588
[35] S. Lee, A.P. Chandrakasan and H. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC with Background Timing Skew Calibration.”, IEEE Journal of Solid-State Circuits 49, 12, 2846-2856, (2014). https://doi.org/10.1109/JSSC.2014.2362851
[36] M. Damghanian and S.J. Azhari, “A novel three-section encoder in a low-power 2.3 GS/s flash ADC.”, Microelectronics J 82, 71–80, (2018). https://doi.org/10.1016/j.mejo.2018.10.009
[37] Yi. Shen and Z. Zhu, “Analysis and optimization of the twostage pipelined SAR ADCs.”, Microelectronics Journal 47, 1–5, (2016). https://doi.org/10.1016/j.mejo.2015.10.018.
[38] Rui Ma, Lisha Wang, Dengquan Li, Ruixue Ding, Zhangming Zhu,“A 10-bit 100-MS/s 5.23 mW SAR ADC in 0.18 μm CMOS.”,Microelectronics Journal 78, 63-72, (2018). https://doi.org/10.1016/j.mejo.2018.06.007
[39] X. Xin et al.,“A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip.”,Microelectronics Journal 83, 104–116, (2019). https://doi.org/10.1016/j.mejo.2018.11.017
[40] W. Guo, S. Liu, and Z. Zhu, “ An asynchronous 12-bit 50MS/s rail-torail Pipeline-SAR ADC in 0.18 μm CMOS.”, Microelectronics Journal 52, 23–30, (2016). https://doi.org/10.1016/j.mejo.2016.03.003
[41] B. Samadpoor Rikan et al.,“A 10-bit 1 MS / s segmented Dual-Sampling SAR ADC with reduced switching energy.”, Microelectronics Journal 70, 89–96, (2017). https://doi.org/10.1016/j.mejo.2017.11.005
Go to article

Authors and Affiliations

Anil Khatak
1
ORCID: ORCID
Manoj Kumar
2
Sanjeev Dhull
3

  1. Faculty of Biomedical Engineering, GJUS&T, Hisar, Haryana, India
  2. Faculty of USICT, Guru Gobind Singh Indraprastha University, New Delhi, India
  3. Faculty of ECE, GJUS&T, Hisar, Haryana, India

This page uses 'cookies'. Learn more